LPUART6 TX(high)/RX(low) all the time in iMX93(9332)

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LPUART6 TX(high)/RX(low) all the time in iMX93(9332)

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sibingl
Contributor I

iMX93(9332 soc),  pinmux the gpio_io04 & gpio_io05 as LPUART6_TX & LPUART6_RX.

dts:

               &lpuart6 {

                               pinctrl-names = "default";

                               pinctrl-0 = <&pinctrl_uart6>;

                               status = "okay";

};

pinctrl_uart6: uart6grp {

                fsl,pin = <

                        MX93_PAD_GPIO_IO04__LPUART6_TX          0x31e

                        MX93_PAD_GPIO_IO05__LPUART6_RX          0x31e

                >;

};

when board power on, /dev/ttyLP5 dev created, but when I test the tx & rx pin, no signal received, and TX high, RX low all the time.

Plus, the BT dev connecting the LPUART6_TX & LPUART6_RX, no CTS&RTS pins exists.

#ls -l /dev/ttyLP*

crw------- 1 root tty     242, 0 Sep 10 18:00 /dev/ttyLP0

crw-rw---- 1 root dialout 242, 5 Sep 20  2023 /dev/ttyLP5

 

I changed the /dev/ttyLP5 group to be tty and I'm sure no gpios occupied by other devs.

Whicherver the termios app(read & write) or stty -F(cat & echo), the /dev/ttyLP5 attr can be saved and succedd to open /dev/ttyLP5, but no signal received by testing the RX&TX pins all the time.

Pls help me out of it or give me some hints or reference doc, Thx

 

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Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @sibingl 

 

I hope you are doing well.

This behavior is expected, because the driver needs the CTS and RTS "definitions".

You can solve adding the fsl,dte-mode:

&lpuart6 {
	compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart", "fsl,dte-mode";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	status = "okay";
};

pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO04__LPUART6_TX		0x31e
			MX93_PAD_GPIO_IO05__LPUART6_RX		0x31e
		>;
	};

 

Then, you will be able to get data from the TX signal:

Alejandro_Salas_0-1726081427921.pngAlejandro_Salas_1-1726081438109.png

 

Remember the default speed is 9800 BPS.

 

Best regards,

Salas.

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Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @sibingl 

 

I hope you are doing well.

This behavior is expected, because the driver needs the CTS and RTS "definitions".

You can solve adding the fsl,dte-mode:

&lpuart6 {
	compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart", "fsl,dte-mode";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	status = "okay";
};

pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO04__LPUART6_TX		0x31e
			MX93_PAD_GPIO_IO05__LPUART6_RX		0x31e
		>;
	};

 

Then, you will be able to get data from the TX signal:

Alejandro_Salas_0-1726081427921.pngAlejandro_Salas_1-1726081438109.png

 

Remember the default speed is 9800 BPS.

 

Best regards,

Salas.

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