FRDM-KL25Z source clock for UART0 in polling mode

[mato_cica1]

Hi NXP Community,

Please, what source clock should I use for UART0 in polling mode on FRDM-KL25Z?
I suppose that should be MCGFLLCLK clock or MCGPLLCLK/2. If so, which on of them?

Thanks in advance,

[jingpan · Accepted solution]

Hi Mato,

It is MCGFLLCLK. UART0 clock source could be the MCG PLL/FLL clock. You can see in to picture that there is no /2 divider in the path.

Regards,

Jing

[mato_cica1]

Thanks a lot, Jing.