FRDM-KL25Z source clock for UART0 in polling mode

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FRDM-KL25Z source clock for UART0 in polling mode

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mato_cica1
Contributor II

Hi NXP Community,

Please, what source clock should I use for UART0 in polling mode on FRDM-KL25Z?
I suppose that should be MCGFLLCLK clock or MCGPLLCLK/2. If so, which on of them?

Thanks in advance,

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jingpan
NXP TechSupport
NXP TechSupport

Hi Mato,

It is MCGFLLCLK. UART0 clock source could be the MCG PLL/FLL clock. You can see in to picture that there is no /2 divider in the path.

pastedImage_1.png

Regards,

Jing

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jingpan
NXP TechSupport
NXP TechSupport

Hi Mato,

It is MCGFLLCLK. UART0 clock source could be the MCG PLL/FLL clock. You can see in to picture that there is no /2 divider in the path.

pastedImage_1.png

Regards,

Jing

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mato_cica1
Contributor II

Thanks a lot, Jing.

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