Does K32L2B31VFM0A/K32L2 include multiplier or not?

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Does K32L2B31VFM0A/K32L2 include multiplier or not?

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Contributor I

1) K32L2B3xRM.pdf, page 51, $3.1: "The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions." Could you please show us these detail three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions? K32L2B31VFM0A, does this chip include multiplier or not?


2) DDI0484C_cortex_m0p_r0p1_trm.pdf, page1-5, $1.4.1 Configurable multiplier, "The MULS instruction provides a 32-bit x 32-bit multiply that returns the least-significant 32-bits of the result. The processor can implement MULS in one of two ways: As a fast single-cycle array. As a 32-cycle iterative multiplier." If yes, for K32L2B31VFM0A, "a single-cycle multiplier, in designs optimized for high performance" or "a 32-cycle multiplier, in designs optimized for low area", which one is inside this chip?

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NXP TechSupport
NXP TechSupport

Hi Jack xiang,

1.  K32L2B3xRM.pdf, page 51, $3.1: "The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions." Could you please show us these detail three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions? K32L2B31VFM0A, does this chip include multiplier or not?

Answer: 

   K32L2B3x is the ARM Cortex M0+ core, from the ARM core document, you can know, the ARM Cortex M0+ core can support the multiplier:

   The following picture is from :The Definitive Guide to the ARM Cortex-M0

pastedImage_1.png

   About the related instructions, you can check the asm code, this is the KE series with the same Cortex M0+ core:

The instructions is muls

2) DDI0484C_cortex_m0p_r0p1_trm.pdf, page1-5, $1.4.1 Configurable multiplier, "The MULS instruction provides a 32-bit x 32-bit multiply that returns the least-significant 32-bits of the result. The processor can implement MULS in one of two ways: As a fast single-cycle array. As a 32-cycle iterative multiplier." If yes, for K32L2B31VFM0A, "a single-cycle multiplier, in designs optimized for high performance" or "a 32-cycle multiplier, in designs optimized for low area", which one is inside this chip?

Answer:  It should be the faster multiplier with single-cycle multiplier, 

This post may also useful to you.

Use of Cortex-M0/M0+ multiply instructions on LPC43xx and LPC5410x 

I also checked the K32L2B3 SDK, which can be downloaded from this link:

Welcome | MCUXpresso SDK Builder 

pastedImage_4.png

You can find the MCU C Complier, architecture select Cortex M0+, not the cortex M0+ small Multiplier with 32 cycles to execute a MULS instruction.

Wish it helps you!

If you still have questions about it, please kindly let me know.

Best Regards,

Kerry

 

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