Hi there,
in the datasheet of the K60 (9/2011) I see that SPI1 is connected to Pins
CS0 --> PTE4
CLK --> PTE2
SOUT --> PTE1
SIN --> PTE3
which are mentioned in "ALT2" configuration.
The example provided in C:\Freescale\Freescale MQX 3.8\mqx\examples\spi\uv4\twrk60n512 is functional in these pins when I activate SPI1 in user_config.h (at least I can see activity with my scope on these pins)
How can I change SPI1 to these pins
CS0 --> PTB10
CLK --> PTB11
SOUT --> PTB16
SIN --> PTB17
which are also mentioned in "ALT2" configuration.
Solved! Go to Solution.
Pin assignment is configured in BSP, for your twrk60n512 that is:
c:\Freescale\Freescale MQX 3.8\mqx\source\bsp\twrk60n512\init_gpio.c
In the _bsp_dspi_io_init(), you need to change:
case 1:
/* Configure GPIOE for DSPI1 peripheral function */
pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;
pctl->PCR[1] = PORT_PCR_MUX(2); /* DSPI1.SOUT */
pctl->PCR[2] = PORT_PCR_MUX(2); /* DSPI1.SCK */
pctl->PCR[3] = PORT_PCR_MUX(2); /* DSPI1.SIN */
pctl->PCR[4] = PORT_PCR_MUX(2); /* DSPI1.PCS0 */
/* Enable clock gate to DSPI1 module */
sim->SCGC6 |= SIM_SCGC6_SPI1_MASK;
break;
to
case 1:
/* Configure GPIOB for DSPI1 peripheral function */
pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;
pctl->PCR[16] = PORT_PCR_MUX(2); /* DSPI1.SOUT */
pctl->PCR[11] = PORT_PCR_MUX(2); /* DSPI1.SCK */
pctl->PCR[17] = PORT_PCR_MUX(2); /* DSPI1.SIN */
pctl->PCR[10] = PORT_PCR_MUX(2); /* DSPI1.PCS0 */
/* Enable clock gate to DSPI1 module */
sim->SCGC6 |= SIM_SCGC6_SPI1_MASK;
break;
And then make sure you disable or re-map other drivers that map onto those pins.
For example, electrodes for TSI are mapped to PORTB_PCR16 and PORTB_PCR17 in _bsp_tss_io_init() function.
Pin assignment is configured in BSP, for your twrk60n512 that is:
c:\Freescale\Freescale MQX 3.8\mqx\source\bsp\twrk60n512\init_gpio.c
In the _bsp_dspi_io_init(), you need to change:
case 1:
/* Configure GPIOE for DSPI1 peripheral function */
pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;
pctl->PCR[1] = PORT_PCR_MUX(2); /* DSPI1.SOUT */
pctl->PCR[2] = PORT_PCR_MUX(2); /* DSPI1.SCK */
pctl->PCR[3] = PORT_PCR_MUX(2); /* DSPI1.SIN */
pctl->PCR[4] = PORT_PCR_MUX(2); /* DSPI1.PCS0 */
/* Enable clock gate to DSPI1 module */
sim->SCGC6 |= SIM_SCGC6_SPI1_MASK;
break;
to
case 1:
/* Configure GPIOB for DSPI1 peripheral function */
pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;
pctl->PCR[16] = PORT_PCR_MUX(2); /* DSPI1.SOUT */
pctl->PCR[11] = PORT_PCR_MUX(2); /* DSPI1.SCK */
pctl->PCR[17] = PORT_PCR_MUX(2); /* DSPI1.SIN */
pctl->PCR[10] = PORT_PCR_MUX(2); /* DSPI1.PCS0 */
/* Enable clock gate to DSPI1 module */
sim->SCGC6 |= SIM_SCGC6_SPI1_MASK;
break;
And then make sure you disable or re-map other drivers that map onto those pins.
For example, electrodes for TSI are mapped to PORTB_PCR16 and PORTB_PCR17 in _bsp_tss_io_init() function.
Tobias,
Both pin assignments are correct.
SPI1 (and other modules) signals are routed to different ports, this enables some flexibility when designing schematics for your application.