Hello,
I'm trying to configure the clock to run at 116 MHz in a MPC5668G with MQX 4.1. I modified the function ClockInit in file __ppc_eabi_init.c as follow:
/* System is clocked by IRC (00 IRC, 01 4-40MHz, 10 PLL)*/
SIU.SYSCLK.B.SYSCLKSEL = 0b00;
/*----- PLL -----*/
/* Enable the 4-40MHz oscilator (not necessary, done by reset) */
CRP.CLKSRC.B.EN40MOSC = 1;
/* Enable clock 128KHz for RTC */
CRP.CLKSRC.B.EN128KIRC = 1;
/* Set ERFD to divide by 5 at first to avoid cpu overclocking -
** should not occur since system is not clocked from PLL
** Set PLL to use crystal reference (12MHz),
** EMFD=100 to multiply by 116,
** and EPREDIV=5 to divide by 6
** Result: fvco = 12MHz * 116 / 6 = 200MHz (192-600MHz)
** fout = 12MHz * 116 / (6 * 5) = 40MHz
*/
FMPLL.ESYNCR2.R=0x00000004;
FMPLL.ESYNCR1.R=0x70050064;
/* Wait for PLL lock (<400us) */
while(FMPLL.SYNSR.B.LOCK != 1);
/* ERFD now divides only by 6 so * fout = fvco / (ERFD+1)
* fout = 12MHz * 116 / (6 * 2) = 116MHz */
FMPLL.ESYNCR2.R=0x00000001;
/*----- SIU - CLK -----*/
/* System is clocked by PLL (00 IRC, 01 4-40MHz, 10 PLL)*/
SIU.SYSCLK.B.SYSCLKSEL = 0b10;
However, it doesn't work. At first instruction executed after having switched system clock to PLL (last line of previous code), I get a trap. When I go step by step in the deassembly view with my debugger, the assembly instructions read by the debugger change which is wird. What's wird too is that I can configure the clock to run up to 84 MHz but at 85 MHz it doesn't work, I get a trap but the assembly code is not modified. In all cases, the CLKOUT signal is OK.
I also tried to activate the frequency modulation with different setting without success.
The clock reference we are using is NX5032GA-12.000M if that helps.
I also tried the PLLinit code in AN4241.pdf but it doesn't work better. Also, is that me or is the function set a PLL at 128 MHz in this application notes?
Anyone can help please?
Thanks!
Hugo
Solved! Go to Solution.
I've ask the question in the MPC5xxx forum and I got a good answer from Lukas Zadrapa:
"
Hi Hugo,
how did you set the flash wait states in PFCRP register? This could be the reason. Follow datasheet and chapter Flash Memory Electrical Characteristic to see how to set the number of wait states.
Or try to execute the code from RAM memory to see if it works.
Regards,
Lukas
"
Hello Hugo,
In order to modify the clock configuration, you need to modify the BSP.
Please check the twrpxn20.h file located at the path: C:\Freescale\Freescale_MQX_4_0\mqx\source\bsp\twrpxn20
In this file you will find the below code
/*----------------------------------------------------------------------
** CLOCK CONFIGURATION
*/
/*
** The processor clock speed
*/
#define BSP_XOSC_CLOCK (40000000)
#define BSP_FMPLL0_CLOCK (80000000)
#define BSP_SYSTEM_CLOCK (BSP_FMPLL0_CLOCK)
#define BSP_CORE_CLOCK (BSP_SYSTEM_CLOCK)
#define BSP_TIMEBASE_CLOCK (BSP_CORE_CLOCK)
#define BSP_PERIPHERAL_CLOCK (BSP_SYSTEM_CLOCK)
#define BSP_PERI1_CLOCK (BSP_SYSTEM_CLOCK/2)
#define BSP_PERI2_CLOCK (BSP_SYSTEM_CLOCK)
#define BSP_PERI3_CLOCK (BSP_SYSTEM_CLOCK/2)
#define BSP_PERI4_CLOCK (BSP_SYSTEM_CLOCK/2)
#define BSP_I2C_CLOCK (BSP_PERI1_CLOCK)
#define SYSTEM_CLOCK (BSP_SYSTEM_CLOCK/1000000) /* system bus frequency in MHz */
/*----------------------------------------------------------------------
Modify it according your needs.
Have a great day,
Sol
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Hello Soledad,
Thank you for your answer. I modified the file twrpxn20.h already but this is only useful to set the OS timer. My software fails right after switching the clock to PLL so much before initializing the OS.
Any other ideas?
Thanks,
Hugo
I've ask the question in the MPC5xxx forum and I got a good answer from Lukas Zadrapa:
"
Hi Hugo,
how did you set the flash wait states in PFCRP register? This could be the reason. Follow datasheet and chapter Flash Memory Electrical Characteristic to see how to set the number of wait states.
Or try to execute the code from RAM memory to see if it works.
Regards,
Lukas
"