S32R274 STM Timer only runs after debug breakpoint

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

S32R274 STM Timer only runs after debug breakpoint

1,133 Views
drainhart
Contributor I

Hello,

I have a weird issue with my STM Timer. Here is my setup: I have the old Dolphin DCC Kit with a S32R274 and a TEF810x and a Matlab skript, which configures a chirp at the beginning and triggers it repeatedly via ethernet. Whenever a chirp triggers I want to measure the time it takes until the acquisition is completed and I want to do some other stuff, every 50µs. I did this using the STM1 timer.

The problem is that the timer only wants to count after I have enabled a debug breakpoint after the line that starts it. Otherwise it seems like the CPU skips its activation. After going through the breakpoint once it works for further chirps without issues. This holds only until I restart the Matlab skript, which reconfigures the chirp again. The chirp configuration only touches MIPI and SPT registers and does communication via SPI (Any waiting in this part is done via NOP loops). Then it gets skipped again until I stop at the breakpoint again.

This is how I programmed the timer and the only place any STM registers are touched (I checked).

void STM1_start(void){
	STM_1.CR.R = 0x0; 			// Disable timer (stop counter)
	STM_1.CNT.R = 0;            // Clear counter.
    STM_1.CR.R = 0x00000001;	// Divide system clock by 1 & enable timer
}

uint32_t STM1_stop(void){

    uint32_t stm_data;

    STM_1.CR.R = 0x0; 			// Disable timer (stop counter)
    stm_data = STM_1.CNT.R;		// Store time results
    STM_1.CNT.R = 0;            // Clear counter.
    return stm_data;
}

uint32_t STM1_get(void){

    return STM_1.CNT.R;
}

And this is how I use it (In Core0 exclusively):

const uint32_t delayTicks = 50 * STM_uSecBase;
uint32_t targetTicks = delayTicks;

StartChirp();//Trigger TEF810x via SPI
STM1_start();
while(Waiting4Chirp()){//Wait until aquisition complete by polling SPT flag
	if(STM1_get() >= targetTicks){
		targetTicks += delayTicks;
		doThings();
	}
}
targetTicks = STM1_stop();
print(targetTicks);

Any help is very appreciated, as I dont even have an idea where to look at anymore.

0 Kudos
Reply
3 Replies

1,109 Views
drainhart
Contributor I

Hello,

See, I did set a breakpoint right after STM1_start(); to see if this point would be reached at all and after the breakpoint was reached and I continued the program, the counter works just fine. It continues to do so without the breakpoint until I reconfigure the chirp via the Matlab script, as mentioned earlier. I might make a video of it later, as the project file is too big and only runs on an old 2017 DCC Dolphin Radar kit, which needs some reconfiguration to work with the newer RDK-S32R274 (If at all). Is there something like an interrupt flag that needs to be cleared before it can start counting or something? Its weird that a debugger breakpoint makes it work and a seemingly unrelated piece of code breaks it again. I was hoping a bit that this was a known quirk or something.

Maybe I can also make a minimum example with an additional variable counting up in the busy loop and waiting until it reaches x to eliminate the TEF810x itself. I will do so later.

0 Kudos
Reply

1,094 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Its weird that a debugger breakpoint makes it work and a seemingly unrelated piece of code breaks it again.

Not at all. Stop on debugger will let your timers catch up. Those whose running will finish (if not set to stop on enter to debug mode), while core is not executing as its break.

If you serve use STM interrupts make sure you clear them.

petervlna_0-1636538508884.png

The STM has four identical compare channels. Each channel includes a channel control
register (STM_CCRn), a channel interrupt register (STM_CIRn), and a channel compare
register (STM_CMPn). The channel is enabled by setting the STM_CCRn[CEN] bit.
When enabled, the channel will set the STM_CIRn[CIF] bit and generate an interrupt
request when the channel compare register matches the timer counter. The interrupt
request is cleared by writing 1 to the STM_CIRn[CIF] bit. A write of 0 to the
STM_CIRn[CIF] bit has no effect.

 

So if you are reenabling the STM in interrupt you should always clear CIF before enabling STM.

Please refer to STM chapter of reference manual.

Best regards,

Peter

 

0 Kudos
Reply

1,114 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

So basically what you are experiencing is that your STM is simply not starting.

This has nothing to do with debugger in my opinion.

Simply your

STM_1.CR.R = 0x00000001;	// Divide system clock by 1 & enable timer

 Is not being executed by core. Set breakpoint / or endless loop after this instruction to see if you can ever reach it.

Or eventually to assembly write execution to STM1.CR. Maybe it is preempted by some interrupt or so.

Best regards,

Peter

0 Kudos
Reply