Dear NXP Support Team:
We had problem developing SPI for MPC5746C.
We hope that 5746C as Slave can communicate with I.MX8 through SPI.
But now I.MX8 can normally send and receive data, but 5746C has problems in both receiving and sending data.
MPC5746C development environment:
IED:S32DS
SDK:S32DS_PA_v2017.R1_UP9 (PS:S32DS_PA_v2017.R1_UP10 met same problem)
Channel:SPI_0:
Clock:PG[13]
SIN/MOSI: PG[10]
SOUT/MISO: PG[12]
SS: PG[11]
Problem:
We want 5746C to transfer 10 bytes of data{0x0D,0x05,0x01,0x00,0x05,0x05.....},But only 4 bytes were seen on the oscilloscope{0x00,0x0D,0x05,0x01,0x00,0x00,0x00,0x00.....}.
The I.MX8 has sent 15 bytes, but the MPC5746C cannot receive them.
In the picture above, the yellow line is CLOCK, the green line is MPC5746C SOUT.
I can't send all the original project, so I put the code related to SPI in the attachment.
In the attached project, the data that 5746C wants to transfer are {55,44,33,22,11,00,99,88,77,66},but all the datas display in oscilloscope is 0x16.
Best Regards
Above is the status register diagram of the attached project, RX&TX FIFO had overflow/underflow.
Hi,
You send just 4 bytes because the CPU is not fast enough to push new data in TX FIFO. The transfer is interrupt by underflow event and the status of your transfer is fail.
To fix this behavior you have the following solutions:
-reduce spi master clock frequency
-use DMA mode
Best regards,
Razvan