RAM ECC and FCCU

[dario_arcaro]

Hi,

I'm working on FCCU for MPC5777C microcontroller and I'm trying to generate correctable/uncorrectable fault on RAM. In order to do this, I've followed the code present in this example:

Example_MPC5777C-1b+2b_RAM_ECC_error_injection-v0_2-GHS614

This code injects 1b/2b ECC errors on the RAM memory by the EIM peripheral and I see the results of the errors in the ERM peripheral but I don't see the signaling toward the FCCU. According to my understanding, I expect that fault number 45 or 46 should be latched in the  FCCU_NCF_S1 register because the same are enabled in the

FCCU_NCF_E1 register.

I have read on this forum another couple of questions about this point but I didn't find a solution or a hint. 

Is there someone that can help me understanding better this situation ?

Thanks in advance.

Dario Arcaro

[davidtosenovjan]

Hi, FCCU has disabled fault reactions by default. As on this device, EIM can generated interrupts directly it was not necessary to configure FCCU for example purposes.

However you may take a look on the following example, the principle is the same. MPC5644P device use MEMU instead of EIM, and FCCU is always involved as 2bECC interrupt reaction is only routed over FCCU:

https://community.nxp.com/docs/DOC-335206 

Also pay attention to following appnote,mainly section 6:

https://www.nxp.com/docs/en/application-note/AN5284.pdf 

[dario_arcaro]

Hi David,

thanks for your reply. I've solved but according to my tests it seems that the fault number 45 and 46 (ERM_CE, ERM_UCE) are latched in the FCCU faults only enabling and handling the ERM ISR. Without this kind of setting I've been not able to trigger ECC faults in the sense that the IVOR1 seems to be triggered and the CE/UCE events seem to be present in the ERM status registers but the faults are not latched in the FCCU. In my opinion this kind of situation is not very clear. Do you agree ?

Dario Arcaro