MPC5744P - SPI change clock polarity between chip selects (CTAR)

[chosp]

I'm interested in connecting two devices to the same SPI bus which differ on the idle clock polarity (defined as CPOL).

The MPC5744P i'm working on provides a clever resource to deal with this, which are the CTAR registers and the CTAS field when performing a TX write.

However, I have a question I've been unable to answer reading through the documentation. 

If transfer #0 is made to CS0 with CPOL=0 (using CTAR0 config), and then transfer #1 is made to CS1 with CPOL=1 (using CTAR1 config):

a) Clock polarization change happens before CS assert (ideal)

b) Clock polarization change happens after CS assert (unfeasible, as the clock change may count as a valid shift)

Please provide me with evidence on documentation of either answer, as this will condition my entire design.

Best regards

[davidtosenovjan]

Hi,

option no.A is correct unless SPI is configured for Continuous Selection Format is selected, in this case polarity change is not allowed.

[chendong]

Hi, I have the same application that two devices connect to one SPI bus with different clk polarity. And I have measured the waveform when two devices communication, as shown below (CS1 is not measured).

I found that CLK will change before CS assert. But the timing does not meet the requirements. Time betwwen CLK change and CS assert is only 10ns, the deviece connect to CS0 require 75ns. This will cause the communication failure. The enlarged waveform is as shown below.

Is there some way to configure the delay after CLK changed?