MPC5644A is out of order after enabling cache,

[Chenlong]

Hi,

I am using MPC5644A and I have already enabled cache. Good news is that the CPU load  decreased from 70% to 40%. However the ADC buffer is confused. I use DMA to move conversion command to ADC core and  move the converted result from ADC core to the buffer array. The buffer array sequense  seems to be smooth shifted  when I enable cache.  I don't know the reason for this phenomenon, and I hope to get your help.

Are there any tips about cache?  if cache is enabled, what should I pay special attention to when writing code ?

[martin_kovar]

Hello,

RAM memory area, which is accessed by DMA should be set as cache inhibited. If you write to RAM using DMA and this part of memory is cachable, it should case some problem.

Please look at the PinToggleStationery example below. There are some functions in optimization.c file, which could help you to set MMU correct.

Example XPC567XRKIT PinToggleStationery CW210 

There is also MMU configuration tool you can easily use

https://community.nxp.com/docs/DOC-331924 

Please try and let me know, if it helps you.

Best Regards,

Martin