The default address of the flash on the board is 0x60000000, but I want to debug my afx file at 0x60100000. T
his is because my bootloader application is written at 0x60000000 and it takes too much time to rewrite it. Therefore, I want to change the address to 0x60100000 and proceed with the debugging process.
However, after changing the base address, writing is successful but debugging fails. Do I need to change the cfx(or scp) file or .ld file? There is no command for the .boot_hdr section in the generated .ld file.
============= SCRIPT: RT1050_connect.scp =============
RT1050 Connect Script
DpID = 0BD11477
APID = 0x04770041
Disabling MPU
Configure FlexRAM for 256KB OC RAM, 128KB I-TCM, 128KB D-TCM
Finished
============= END SCRIPT =============================
Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V2.250 (NXP Semiconductors)
Serial Number: N1MRPGLLIAIJT
VID:PID: 1FC9:0143
USB Path: \\?\hid#vid_1fc9&pid_0143&mi_00#8&253ee304&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}
Using memory from core 0 after searching for a good core
debug interface type = CoreSight DP (DAP DP ID 0BD11477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 0BD11477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0)
ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BB9A9 CSt type 0x11 Trace Sink - TPIU
ROM 1 E0043000: CID B105F00D PID 04001BB101 Sys (type 0x0)
NXP: MIMXRT1052xxxxB
DAP stride is 1024 bytes (256 words)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1050_SFDP_QSPI.cfx
Image 'iMXRT1050_SFDP_QSPI Dec 16 2021 12:43:11'
Opening flash driver MIMXRT1050_SFDP_QSPI.cfx
Sending VECTRESET to run flash driver
Flash variant 'JEDEC_SFDP_Device' detected (64MB = 1024*64K at 0x60000000)
Closing flash driver MIMXRT1050_SFDP_QSPI.cfx
Connected: was_reset=false. was_stopped=true
Awaiting telnet connection to port 3330 ...
GDB nonstop mode enabled
FreeRTOS stack backtrace is disabled in Non-stop mode (use All-stop)
Opening flash driver MIMXRT1050_SFDP_QSPI.cfx (already resident)
Sending VECTRESET to run flash driver
Flash variant 'JEDEC_SFDP_Device' detected (64MB = 1024*64K at 0x60000000)
Writing 19022672 bytes to address 0x60100000 in Flash
60108000 done 3% (32768 out of 1048576)
As you can see in the above , JEDEC_SFDP_Device appears as 0x60000000 after the scp file. Please let me know how to proceed.
Hi @abs_setian
My apologies for the delayed response.
I understand that you want to debug your XIP image living and this address 0x6010_0000.
For debug purposes, I would link the application to RAM. This would be easy. Easiest method is linking to internal SRAM ( OCRAM, ITCM , DTCM). MCUXpresso does support this option and enables easy debug for this.
If the application cannot fit into internal SRAM, I would use an external SDRAM. This post links how to create enable SDRAM debug. See the answer in this post RT1170 debugging when application is built for SDRAM
You can load your application at 0x6010_0000 let your bootloader to jump to the application and then manually attach the debugger when the application is executing. MCUXpresso should let you do this. I understand that you are using MCUXpresso when you mentioned about the scripts
Now, if you really do not want to use the bootloader and debug the application at start
However, the IVT does need to always be placed at 0x6000_1000. The bootROM will always search the IVT at this address when attempting to boot XIP images. So, you may need to overwrite the bootloader space, in this scenario. This video introduces boot flow, IVT and other elements of bootable images shortly and nicely NXP: MCU Tech Minutes: Boot Options for i.MX RT Crossover MCUs. If you want to follow this path, let me know, so I can give you more information.
I hope this helps!
