yes, i connected DDRv tool to my target board,and "start validation", but it is Execution failed and will not proceed。I tried several times but still failed.
The attachment is the log, but the previous contents seem to have been flushed out..
There was a mistake at the beginning：
this is the Error capture registers values...there valuse are all 0x0
AS the following figure。there is a Lead-in paramter , don't know how to fill in this parameter, How do I get this parameter？
Thank you for your reply
Does the DQ mapping need to be configured? my dram type is discrete...
I configured the above values based on the hardware's CLK To DQS parameters, and then generated the code in CodeWarrior, i Copy the static_1600 to my source code
const struct ddr_cfg_regs static_1600 = {
.cs[0].config = 0x80010412,
.cs[0].bnds = 0xFF,
.sdram_cfg[0] = 0x65240000,
.sdram_cfg[1] = 0x00401030,
.timing_cfg[0] = 0x8055000C,
.timing_cfg[1] = 0x0A0E0C42,
.timing_cfg[2] = 0x0048D11C,
.timing_cfg[3] = 0x11511000,
.timing_cfg[4] = 0x01,
.timing_cfg[5] = 0x05401400,
.timing_cfg[7] = 0x23340000,
.timing_cfg[8] = 0x07116600,
.sdram_mode[0] = 0x01010234,
.sdram_mode[9] = 0x0701,
.sdram_mode[8] = 0x00,
.sdram_mode[2] = 0x00,
.sdram_mode[10] = 0x04000000,
.sdram_mode[11] = 0x00,
.sdram_mode[4] = 0x00,
.sdram_mode[12] = 0x00,
.sdram_mode[13] = 0x00,
.sdram_mode[6] = 0x00,
.sdram_mode[14] = 0x00,
.sdram_mode[15] = 0x00,
.interval = 0x18600618,
.zq_cntl = 0x8A090705,
.wrlvl_cntl[0] = 0x00,
.wrlvl_cntl[1] = 0x00,
.wrlvl_cntl[2] = 0x00,
.debug[28] = 0x01080F70
};
After compiling with the flex-builder -c atf -m lx2160ardb_rev2 -b xspi command, bl2_flexspi_nor.pbl and fip_uboot.bin,programmed it to the Flash, but it still prompts the 2D Training .(I turned on the Debug switch).Debugging several days, all the time not to the main point
The following is the log information, looking forward to your reply...
NOTICE: BL2: v2.3():v2.3-LSDK-20.12-dirty
NOTICE: BL2: Built : 16:15:55, May 18 2021
platform clock 800000000
DDR PLL1 1600000000
DDR PLL2 1600000000
frequency = 800MHz
Vref_phy = 75 percent
Initializing input adv data structure
mr[0] = 0x234
mr[1] = 0x101
mr[2] = 0x0
mr[3] = 0x0
mr[4] = 0x0
mr[5] = 0x0
mr[6] = 0x0
input->cs_d0 = 0x3
input->cs_d1 = 0x0
input->mirror = 0x0
PHY ODT impedance = 48 ohm
PHY DQ driver impedance = 28 ohm
PHY Addr driver impedance = 30 ohm
odt[0] = 0x1
odt[1] = 0x0
odt[2] = 0x0
odt[3] = 0x0
Initializing message block
msg_blk->dram_type = 0x2
msg_blk->sequence_ctrl = 0x31f
msg_blk->phy_cfg = 0x0
msg_blk->x16present = 0x3
msg_blk->dramfreq = 0x640
msg_blk->pll_bypass_en = 0x0
msg_blk->dfi_freq_ratio = 0x2
msg_blk->phy_odt_impedance = 0x0
msg_blk->phy_drv_impedance = 0x0
msg_blk->bpznres_val = 0x0
msg_blk->enabled_dqs = 0x48
msg_blk->acsm_odt_ctrl0 = 0x1
msg_blk->acsm_odt_ctrl1 = 0x0
msg_blk->acsm_odt_ctrl2 = 0x0
msg_blk->acsm_odt_ctrl3 = 0x0
rx2d_train_opt 0, tx2d_train_opt 0
Initialize PHY 0 config
pll_ctrl2 = 0xb
SOC_SI_REV = 2
dll_lck_param = 0x212
dll_gain_ctl = 0x61
acx4_anib_Dis 0x0
Load 1D firmware
Loaded Imaged id 32 of size 6bd0 at address 18003000
Loaded Imaged id 34 of size 6d0 at address 18003000
Execute firmware
Applying PLL optimal settings
pll_ctrl2 = 0xb
pll_ctrl1 = 0x21
pll_test_mode = 0x24
pll_ctrl4 = 0x17f
End of fine write leveling
1D Training completed
Error - Invalid cs_in_use value 0
CDD rrmax 3 wwmax 4 rwmax 2 wrmax 0
Load 2D firmware
Loaded Imaged id 33 of size 694c at address 18003000
Loaded Imaged id 35 of size 5bc at address 18003000
Execute 2D firmware
Applying PLL optimal settings
pll_ctrl2 = 0xb
pll_ctrl1 = 0x21
pll_test_mode = 0x24
pll_ctrl4 = 0x17f
End of initialization
End of initialization
End of initialization
2D Training failure
ERROR: Execution FW failed (err -5)
Program controller registers
twopass=0
PHY handshake timeout..., ddr_dsr2 = 0
total size 4 GB
Need to wait up to 1320 ms
ERROR: Found training error(s): 0x100
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
NOTICE: Incorrect DRAM0 size is defined in platform_def.h -5
