LS2088ARDB How I can use ProcessorExpert DDR to validate my DDR

[benoitmasse]

Hi, 

First, I used the original code in NOR flash and the original DDR. 

I used Processor Expert to retrieve the actual Data from my ls2088ARDB.

Import DDR controler 1 and 2 from target, and import PBL, Read from Target.

Than I run the first test and it failed. (Write-Read Compare)

I want to use this tool to integrate Micron 18ASF2G72AZ-2G6E2, but I cannot do basic thing with the actual. Any help will be appreciate.

#################### Result for: wrlvl_searcher ###### Run 1 ######################################

Test result: [
============================================================
Updated: WRLVL_CNTL = 0x86750605, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================
Updated: WRLVL_CNTL = 0x8675060A, WRLVL_CNTL_2 = 0x0B0C0D10, WRLVL_CNTL_3 = 0x0A0B0C0E, SDRAM_CLK_CNTL = 0x02800000

============================================================
Updated: WRLVL_CNTL = 0x8675060A, WRLVL_CNTL_2 = 0x0B0C0D10, WRLVL_CNTL_3 = 0x1113140E, SDRAM_CLK_CNTL = 0x02800000

DDR interface is failing due to an issue other than WRLVL_START values, please investigate HW issues on the board.
<<Test failed!>>
{{DDR interface is failing due to an issue other than WRLVL_START values, please investigate HW issues on the board.}}

Err. capture registers:
0xE20, 0x55555555 0xE24, 0x55555555 0xE28, 0x00000000 0xE40, 0x00000000
0xE44, 0x00000000 0xE48, 0x00000000 0xE4C, 0x60FF2001 0xE50, 0xFFFFFEC0
0xE54, 0x00000003 0xE58, 0x00010000

Dump:
0xF00, 0x00000000 0xF04, 0x00000002 0xF08, 0x0000000C 0xF0C, 0x14000C20
0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000
0xF20, 0x00000000 0xF24, 0x3D004100 0xF28, 0x43004500 0xF2C, 0x4C004E00
0xF30, 0x51005300 0xF34, 0x48007000 0xF38, 0x00000000 0xF3C, 0x00000000
0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0xD4000000
0xF50, 0x14001600 0xF54, 0x18001A00 0xF58, 0x21002400 0xF5C, 0x27002800
0xF60, 0x1D000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000
0xF70, 0x00700076 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000
0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000
0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x31003000
0xFA0, 0x31003000 0xFA4, 0x31003000 0xFA8, 0x30003100 0xFAC, 0x30000000
0xFB0, 0x10000003 0xFB4, 0x50454445 0xFB8, 0x45454544 0xFBC, 0x45454345
0xFC0, 0x44454544 0xFC4, 0x45444445 0xFC8, 0x45455043 0xFCC, 0x45444450
0xFD0, 0x50455045 0xFD4, 0x44444450 0xFD8, 0x44504544 0xFDC, 0x50444550
0xFE0, 0x45504544 0xFE4, 0x44444345 0xFE8, 0x45454543 0xFEC, 0x50444550
0xFF0, 0x50505045 0xFF4, 0x45504550 0xFF8, 0x51505050 0xFFC, 0x50000000

Data:
0x00000005 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000

]

[yipingwang]

Please refer to https://community.nxp.com/t5/Qonverge-Knowledge-Base/DDR-Controller-Configuration-on-LS2085-LS2080-B...

You need to create a QCVS DDR project with the method "reading from SPD", then use DDRv tool to connect to the target board to initialize DDR controller, validate and optimize the DDR configuration by gradually refining.

[benoitmasse]

I did that, my problem it's when I'm trying to validate the second controller.

If I activate one controller with one UDIMM 18ASF2G72AZ-2G6E2 (DDR_Controller_1) everything is fine.

When I do the same process with both Controller (1 and 2) with two UDIMM 18ASF2G72AZ-2G6E2, The validation cannot find the right WRLVL value to start.

I got a similar problem when I adapt the DDR for "Target Initialization File" for Target Connection.

I take the ddrCtrl_1,py and ddrCrtl_2.py generated by the tool (QCVS) and add them to the "Target Initialization File". Run the "Diagnose connection" and the test failed the first time. Then I added the following lines

CCSR_LE_M(0x1080000 + id * 0x10000, 0x7ff)
CCSR_LE_M(0x1080008 + id * 0x10000, 0x7ff)
CCSR_LE_M(0x1080010 + id * 0x10000, 0x0)
CCSR_LE_M(0x1080018 + id * 0x10000, 0x0)
CCSR_LE_M(0x1080080 + id * 0x10000, 0xa8050422)
CCSR_LE_M(0x1080124 + id * 0x10000, 0x1c70071c)

for each Controller (id = 0 or 1),

With these modifications the "Diagnose Connection" pass with out error (Target Connections View). Then DDR is programmed correctly.

See the code in attachment file (Micron32G_targetinitialisation.py).

I tried to change the 3FF to 7FF for both controller in the tools (QCVS DDR) but no luck.

Any suggestion ?

[yipingwang]

After creating a QCVS DDR project with reading from SPD method. Please configure "Device" value as "DDR_Controller_2", "DDR Bus Clock" as 933MHz(according your target board) in Properties panel. Please refer to the attachment.

Then in the Validation panel perform "Centering the clock" validation.

If your problem remains, please open CCS(CodeWarrior Connection Server) console, type "log v", then connect to the target board and capture the CCS console log to me to do investigation.

In addition, would you please send your QCVS DDR project to me, I will connect it to my demo board to do more verification?

[benoitmasse]

CCS console, I'm running under ubuntu 20.04 (linux) and I cannot figure out how to enable console neither than run "log v". 

I made a special Workspace with all the code and configuration that I use to test Memory, (One UDIMM or 2 UDIMM , 

I tested connection with the target (In "Target Connections" with USE_SAFE_RCW = True, Connection file is "LS2088A_RDB Benoit V2 G32").

I tested Baredboard in DDR and in OCRAM, everything are fine.

I tested DDR "Centering the clock" with Micron16G (One UDIMM), is OK.

I tested DDR "Centering the clock" with Micron32G (Two UDIMMs), is Not OK.

[benoitmasse]

What thing to mention is, the DDR controler (1 and 2) are programmed in interleaving mode. 

It's the reason I had to add 0x7FF instead of the 0x3FF in the "Target Initialization File".

[yipingwang]

I discussed this issue with the application team, please refer to the following feedback from them.

This issue is tool related and we are in process of determining a fix. for now, Customer can configure each controller individually first. then when running the two controller in QCVS tool bypass (gray out) the auto search (the first cell/table) in the centering the clock test and that will resolve the issue for running validation with two controllers enabled.

[benoitmasse]

Thanks for the answer,

But How can I bypass (grey out) the auto search ?

[yipingwang]

1.   Select the gray square icon to de-select all the cells (inverted queued cells)
2.   Select the white square with gray dashed boarder icon to select a cell or drag to select a group of cells. To select more cells select the same icon again.
3. To clear all selections, select the blue square icon.

[benoitmasse]

I select to queue all tests (or cells) in Centering the clock scenario except the Autos eaerch.

All tests run well but only with my first controller DDR_mc1.

When I start the test with the second controller, DDR_mc2, the test stop right away with any message.It 

Is it normal ?

[yipingwang]

Please start a new project and just test the DDR_mc2.

If this is a board bring up. make sure to check, voltage (GVDD/VREF/VTT), clock(input clock, PLL setting in RCW, and output MCK), reset (the DRAM reset signal needs to match the assertion and de-assertion of the HRESET signal).

also check the DQ_MAP registers. so that the correct mapping is used.

I have verified LS2088ARDB works well with QCVS on both DDR controllers.

[benoitmasse]

FYI: I'm using the eval board ls2088ardb, with the two UDIMM UDIMM 18ASF2G72AZ-2G6E2 for 32Go.

These UDIMMs came with the eval.

I followed your instructions to enable controller 2.

I made a new project.

Configure the controller 2 alone.

In "Component Inspector -DDR" view.

I selected "Validation stage" then Start Validation.

Centering and Read ODT passed.

Write ODT and Operation DDR test failed.

I joined two files, one for controller 1 (all tests passed) and one for controller 2, with some failed.

[ufedor]

At the end of January new version of QCVS (4.23) was released.

Could you please update, create new QCVS project and run the DDR Tool Validation?

[yipingwang]

When you create a QCVS DDR project for the 2nd DDR Controller following new project wizards, in "DDR configuration" panel , please configure "2nd DDR Controller", select Configuration mode as "Read SPD", please refer to the attached screenshot.

I have connected my LS2088ARDB demo board to verify the 2nd DDR Controller validation, all passed.

[benoitmasse]

I updated the tools.

Then I created a new project, I read configuration from target (not from SPD) for both Controllers and run the tools.

All validation tests have been passed successfully.

But I did not try the eye tests.