chip ls1046 with DDR 8G (16bit*1G *4chip) .ECC*1
I'm not sure if my calculation is correct:
1.CK_C =62.723mm. CK_T=62.722mm (Length of copper wire between ls1046 and DDR on PCB)
2.LDQS_C=45.661.LDQS_T=45.782
3.UDQS_C=48.758.UDQS_T=48.750
4.Select one of the groups:CK_C-LDQS_C. CK_C-UDQS_C.
5.get result: 17 14...
one chip of DDR:
new Codewarrior project:
I have a clarification question:
Assuming that a CK is routed from the source to DRAM0 and then terminates at DRAM1, would the skew calculation for DRAM0 be (CK length at DRAM1)- (DQS at DRAM0)? Or (CK length at DRAM0)- (DQS at DRAM0)?
Thanks!
Hi @Hmc510,
Yes, it is the length difference between the clock signal and strobe signal connected to each memory chip.
Regards,
Mrudang