LS1043 ddr4 bit swap in nibble only ?

[stefanvranken]

Hello,

Concerning pcb-layout of LS1043 with 3 discrete ddr4 memories.

LS1043-ddr-controller = 32-bit >> 4 bytelanes wired to 2 sdrams  MT40A512M16

4-bit ECC  (1 parity bit per bytelane) >> wired to 3rd sdram MT40A512M16

AN5087 hardware and layout design considerations for DDR4 sdram memory interfaces, Rev.2, 07/2019

Table 1, Routing databus, no-27 states

- bit-swap is only allowed within a nibble (group of 4 bits)

- bit-swap across 2 nibbles is not allowed

- it is allowed to swap 2 nibbles of a bytelane 

Why is there a restriction on nibble-level ? 

Does this restriction apply when i am using x8 or x16 sdram devices ?

I would expect that bit-swapping is possible within a bytelane (8-bits) because strobe DQS = per bytelane ??  Just as with DDR3 ?

Regards,

Stefan

[stefanvranken]

thanks Ufedor and Cyril,  DDR-DQ-map registers  clearly shows nibble-bit-swap-restriction

I am using discrete DDR4 chips

LS1043 DDR has 32-bit data >>  enter my board-layout bit-swaps into DDR-DQ-map[0]+[1]  DQ_0_31

LS1043 DDR has 4-bit ecc  >>  enter my board-layout bit-swaps into DDR-DQ-map[3]  ECC_0_3

If working with SODIMMs then their bit-swaps (swizzling) must be accounted for also.

[stefanvranken]

The bit mapping is required for controller to perform bit level training (for read and write DQS centering and other training in data bus).

The restriction on bit swizzling is adopted from same JEDEC bit swap restriction used for CRC.

>> For my understanding, do you have some documentation that describes ddr4 nibble bit-swap restriction or bit-level training ?   Jedec-ddr4-spec cannot be downloaded but must be bought.... 

[ufedor]

Bit swizzling restriction for the NXP DDR4 controller implementation is described in the AN5097.

Bit-level training details are confidential and not disclosed to customers.

[stefanvranken]

MT40A512M16 datasheet  shows feature "write crc over data"

LS1043_ARM_v5  reference manual  >>  search for "write crc"  finds results in chapter 22 [SDHC} only ?

[ufedor]

The CRC Write Data Feature is not supported.

[stefanvranken]

Understood.

And LS1043 ddr4-controller does not support feature "write-crc (over 72-bit data)" ?

[ufedor]

> feature "write-crc (over 72-bit data)"

Wich document you are referring?

[stefanvranken]

so if ddr4 feature "write crc (over bytelane)" is enabled, then bit-swapping is restricted to within 4-bit nibble, right ?

And if ddr4 feature "write crc" is disabled,  then this restriction must not be followed ? 

[cyrilstrejc]

If you swap DDR4 data bits, you have to fill in DQ mapping registers of DDR controller, otherwise link training fails. But the DQ mapping settings is supported only for the conditions mentioned above. You can check LS1043A Ref. Man., DQ mapping settings section. This match JEDEC standard.

[ufedor]

The restriction must always be followed.

[ufedor]

For DDR4 only when bits are swapped across the nibble (swizzled), memory controller fails to perform initialization.

The bit mapping is required for controller to perform bit level training (for read and write DQS centering and other training in data bus).

The restriction on bit swizzling is adopted from same JEDEC bit swap restriction used for CRC.
Bit swap rule applies to all DDR4 DRAM (x8, x16).