Is there a typo in Errata A-010840 for the LS1021A

[raymondhaas]

I have been analyzing the Errata for the LS1021A processor, LS1021ACE, Rev. 10, 11/2018.  Specifically, I am looking at the workaround for A-010840. The workaround mentions a register bit DMR[SO].  I have looked in the reference manual, LS1021ARM Rev. 3 10/2018, and there is no bit called SO associated with this register. I was looking in section 30.2.1.2.

Is this a typo?  Am I misreading this?

[ufedor]

I will provide response through the dedicated Technical Case.

[raymondhaas]

I am sorry. I posted this question minutes before I receive an answer from NXP support. I posted the question to NXP support on Feb 5th and didn’t receive an answer. I thought I would try the community site. Please disregard the question. Thank you

[ufedor]

The bit is shown as reserved in the RM.

The DMR[SO] is bit 3.