Hang up at loading image id=3

[__OTL__]

Hi

The Log is as below

NOTICE: Fixed DDR on board
INFO: Time after parsing SPD 5 ms
INFO: Time before programming controller 8 ms

NOTICE: 8 GB DDR4, 64-bit, CL=16, ECC off
INFO: Time used by DDR driver 418 ms
NOTICE: BL2: v1.5(debug):LSDK-20.12-dirty
NOTICE: BL2: Built : 15:30:51, Oct 26 2022
INFO: Configuring TrustZone Controller
INFO: Value of region base = ffe00000
INFO: Value of region base = 1ffe00000
INFO: Value of region base = fbe00000
INFO: Value of region base = a80000000
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xfbe00000

And it just stops there.

The board custom board refered to FRWY1046A and the FIP.bin is made by 

make PLAT=ls1046afrwy fip BL33=/flexbuild_lsdk2012/packages/firmware/u-boot/u-boot.bin DEBUG=1

Could you give some advices?

[__OTL__]

Hi yiping

After changing DDR configuration several times we got this, it stuck at bl31 jumping to u-boot

INFO: RCW BOOT SRC is QSPI
INFO: RCW BOOT SRC is QSPI
INFO: Time before programming controller 0 ms
WARNING: Warning: Optimal CPO value not set.
WARNING: Warning: A009942 requires setting cpo_sample to 0x47

NOTICE: 2 GB DDR4, 64-bit, CL=11, ECC off
INFO: Time used by DDR driver 930 ms
NOTICE: BL2: v1.5(debug):LSDK-20.12-dirty
NOTICE: BL2: Built : 15:18:08, Oct 28 2022
INFO: Configuring TrustZone Controller
INFO: Value of region base = ffe00000
INFO: Value of region base = 1ffe00000
INFO: Value of region base = fbe00000
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xfbe00000
INFO: image size = 50756INFO: test 3.5
INFO: Image id=3 loaded: 0xfbe00000 - 0xfbe0c644
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x82000000
INFO: image size = 774748INFO: test 3.5
INFO: Image id=5 loaded: 0x82000000 - 0x820bd25c
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xfbe00000
NOTICE: BL31: v1.5(debug):LSDK-20.12-dirty
NOTICE: BL31: Built : 20:38:46, Oct 27 2022
NOTICE: Welcome to LS1046 BL31 Phase
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
WARNING: BL31: cortex_a72: CPU workaround for 859971 was missing!
INFO: BL31: cortex_a72: CPU workaround for cve_2017_5715 was applied
INFO: BL31: cortex_a72: CPU workaround for cve_2018_3639 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x82000000
INFO: SPSR = 0x3c9

Two questions 

1. Can we say DDR config is good becasue these is no failure info about DDR in BL2?

2. After jumping to u-boot there is not any log output. 
   Does any misconfig of u-boot cause this?
  Next thing we should do is to optimize the u-boot config is that right?

[yipingwang · Accepted solution]

1.  Yes, DDR can work in atf.

2. You could refer to the document to debug u-boot.

https://community.nxp.com/t5/CodeWarrior-for-QorIQ-Knowledge/Use-CodeWarrior-for-ARMv8-to-Debug-U-bo...

[__OTL__]

After adding some debug print into the bl_common.c 
I found the program is stuck at  

io_result = io_read(image_handle, image_base, image_size, &bytes_read);

Is this a DDR problem?

[yipingwang]

BL2 initializes the DRAM, then loads BL31, BL32, and BL33 images to the DDR memory after validating these images BL31, BL32, and BL33.

According to your error log, it seems that DDR controller initialization section provided in ATF is not suitable for your custom board.

In ATF source code flexbuild_lsdk2108/components/firmware/atf, please modify atf/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c according to your custom board.