Content originally posted in LPCWare by bavarian on Tue Sep 24 05:36:15 MST 2013
The diagrams in the I2S chapter show PLLAUDIO as input into the MCLK path. The naming PLLAUDIO in the figures is misleading. It implies that it is the output frequency of the audio PLL. In fact it is the frequency BASE_APLL_CLK --> PLLAUDIO = BASE_APLL_CLK. And by default BASE_APLL_CLK is set to IRC (= 12 MHz).
I think this is what you see, it is really the PCLK.
You need to connect BASE_APLL_CLK to the output of the Audio PLL (in register 0x400500C0), then you will see this frequency on the TX_MCLK as well.
The register settings in Table 879. Transmitter master mode (PLLAUDIO) are correct, the description in register TXMODE is not (says reserved).
Regards,
NXP Support.