SGPIO Features?

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sat Mar 07 20:22:14 MST 2015
I am still trying to get my head round the SGPIO, specifically on the 4370.

I have fundamental questions.
Imagine a peripheral that takes a clock input and a bi-directional data line.
[Not necessarily partitioned in 8 bit chunks.]

[1] Can the SGPIO be configured to drive/read a bi-directional pin as part of a single transaction?
[2] Can the SGPIO issue 'line turn around' clock(s) without reading or writing the data pin?
[3] Can the SGPIO handle variable direction change point(s)?

I would guess that it can, because it can emulate I2C. But I have not tracked down example code yet.
Any links would be appreciated.

Regards, Mike

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Mar 26 05:11:27 MST 2015
Thanks for that, I will definately read these when I can squeeze some relaxation time.
Mike

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Wed Mar 25 18:30:25 MST 2015
Hi, MikeSimmonds,
Attached are some good stuff you can read about setting a bidirectional pin for I2C operation.
regards,

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Tue Mar 10 10:49:43 MST 2015
Thanks for the hints.

The whole chapter is still a bit over my head, but I will persevere and try to fit your help in
there somehow.

Mike

[lpcware]

Content originally posted in LPCWare by starblue on Tue Mar 10 01:47:33 MST 2015

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Quote: MikeSimmonds

Looks like I need to find additional app notes or examples
So far I have found AN11275 and AN11351.

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There's also AN11343 (and an older version AN11196), probably not too helpful. I'm not aware of an I2C example.

In the UM there is one sentence about I2C in the SGPIO chapter: "Use oe path as data, tie the output data to 0."  Which makes sense, that way you get the open-collector-like behavior needed for I2C. So I guess you are supposed to just shift out the data you need and send 1 bits where you want to read data. And shift in from the same pin into another slice. Afterwards the processor can make sense of the whole. That should for the master, but I don't know whether it could be extended to work for a slave. Maybe you could use a match interrupt to set the slice count disable register.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Mar 09 10:42:11 MST 2015
Thanks so much for you reply.

The UM reference is all very well if you understand it already.
Looks like I need to find additional app notes or examples
So far I have found AN11275 and AN11351.
Isn't there supposed to be an I2C example somwhere.

Re [3] in OP, this because read vs write transaction phases differ.

I guess I need to get some more background on 'qualifier'.

Regards, Mike

[lpcware]

Content originally posted in LPCWare by starblue on Mon Mar 09 03:37:57 MST 2015
Looks like it can do [1] and [2]. I doubt it can do [3] (it is unclear what you want to do, variable depending on what?).

You can configure output enable via OUT_MUX_CFG, bits P_OE_CFG.

To selectively enable reading you can use a qualifier, to enable the clock for your input slice.

In both cases you need to put the pattern for enabling output or input into some other slice.

Note that I only have experience with the qualifier part, and I have only used it for SPI input.