Reset fails because chip not completely reset

[lpcware]

Content originally posted in LPCWare by samc77 on Sun Jul 20 23:57:30 MST 2014
Hi,

we are using a LPC4330 and boot from SPIFI. We have also connected SDRAM.
The problem now is, that whenever the chips resets, no matter if intentional by RGU, by watchdog or by brownout: the periperals dont get reset.
That means, that the SCU, GPIO keep in their last state and that prevents the A9/P2_7/ISP pin from being high level on bootup.
Clearly, because the EMC is still in control of the pin, and depending what it currently does, the A9 line may be hi or lo.

For intentional reset and watchdog reset we already build a workaround and reset the GPIO+SCU manually.

But for a brownout reset, we would have to catch the BOD irq. We didnt manage to do that jet.

Still, this is a lot of workarounds for a problems thats basically in the chip, why doesnt it reset completely? How can we make it reset? I just found some snippets that its related to debug beeing enabled. But no information on how to disable debug for our configuration...

Hope anybody can help on this..

Thanks,
Simon

[lpcware]

Content originally posted in LPCWare by mc on Fri Jul 25 14:50:18 MST 2014
Hi Simon,
Both lines are correct and  there is no typo. Reset control register address is 0x4005 3100 and memmap register address is 0x4004 3100.
Check  page 128/1420 and 213/1420 UM10503 Rev. 1.8 — 28 January 2014.

[lpcware]

Content originally posted in LPCWare by samc77 on Mon Jul 21 23:23:44 MST 2014
Hi,

thanks for your quick answer.

for the intentional reboot, we are doing it very similiar to your version. (I think there is a typo, should be 0x40053100 for both lines, right?)

Doing it exactly your way didnt work for some reason, but replacing the Core Reset by a WDT reset works.

Surely, its not enough to reset the GPIO and ETHERNET, instead its GPIO, SCU and not sure if needed: EMC. (If the SCU is not reset, the pin FUNC will stay at EMC and it will keep in control over the pins)

So our code is this:

    // reset the SCU, EMC, GPIO
    // this is required to make sure that the pins A6 and A9 are hi level during reset.
    // if they are not, the system will not boot from SPIFI and instead end up in the ISP mode
    LPC_RGU->RESET_CTRL0 = (1<<9) | (1<<21) | (1<<28);

  wdt_reset();

  __disable_irq();
  __disable_fault_irq();

  st_Wdt_Config w;

  w.wdtReset = 1;
  w.wdtProtect = 0;
  w.wdtWarningVal = 0;
  w.wdtTmrConst = 10000;

  WWDT_Init();
  WWDT_Configure(w);
  WWDT_Start();

  while(1);


That works reliably.

BUT: if a watchdog timeout occurs, normally, the reset is triggered directly. That will cause the chip to enter the ISP most of the time.
Now, we catch the WDT IRQ and disabled the WDT RESET. That works again.

But will not work in case IRQs are disabled, and that happens to be at some parts of the code.

So its not a real solution, just a 90% workaround.

So my question still is: is it possible to force the chip into the "normal" operation mode, not debug, where it really resets completely on WDT reset?

Thanks,
Simon

[lpcware]

Content originally posted in LPCWare by mc on Mon Jul 21 17:25:31 MST 2014
Hi Simon,
You can have pullup on ISP pin and you can use following instructions to reset the device.
*(volatile unsigned int *)0x40043100 = 0x10400000; //memmap with boot ROM address
*(volatile unsigned int *)0x40053100 =(1<<0); // Core reset