Problem with 4357 USB1 with external phy

[lpcware]

Content originally posted in LPCWare by toad on Thu Apr 23 15:26:34 MST 2015
I have a LPC 4357 connected to a cypress CY7C68003 device only ULPI interface (TX2) on USB1. I configure it using logic similar to that described in app note AN1309 (see below)

It appears that the  CY7C68003 also requires some custom configuration. From the cy7c68003 app note  AN42266:

After reset use the ULPI RegWrite command to initialize the TX2 device in full speed mode and enable the USB interface:
1  Write 0x45 to Function Control Register (0x4)
2. Write 0x0 to Interface control register (0x7)
3. Write 0x4 to USB Interface Control Register (0x35)

I believe I can do this using the LPC viewport:

ret = USBD_API->hw->Init(&g_hUsb, &desc, &usb_param);
UlpiRegWrite (0x4,0x45);
UlpiRegWrite (0x7,0);
UlpiRegWrite (0x35,0x4);

which results in
USBD_API->hw->Init USB1 returncode=0 g_hUsb=100894a8
register dump
UlpiReg[0x00]=0xB4
UlpiReg[0x01]=0x04
UlpiReg[0x02]=0x03
UlpiReg[0x03]=0x68
UlpiReg[0x04]=0x45
UlpiReg[0x07]=0x00
UlpiReg[0x0A]=0x00
UlpiReg[0x0D]=0x00
UlpiReg[0x10]=0x00
UlpiReg[0x13]=0x00
UlpiReg[0x14]=0x00
UlpiReg[0x15]=0x01
UlpiReg[0x16]=0x55
UlpiReg[0x19]=0x00
UlpiReg[0x1D]=0x00
UlpiReg[0x20]=0x00
UlpiReg[0x21]=0x00
UlpiReg[0x31]=0xA0
UlpiReg[0x32]=0x80
UlpiReg[0x33]=0x00
UlpiReg[0x35]=0x04
UlpiReg[0x36]=0x00
UlpiReg[0x39]=0x00


Following on, the cypress app note states that when the TX2 connects to the host and the host initiates a reset sequence and the TX2 sends the updated line state in a RX CMD to the controller. "To enable chirp signaling, the controller must write 0x54 to the Function Control Register and then initiate a NOPID transmit sequence". My question is, does the ROM code do any of this? and if not is there a way a can detect the line status update and send a NOPID transmit sequence ?


static void ULPI_USB1_init( void )
{
    uint32_t  portsc;

    /* disable USB1_CLOCK, it's clock will be provided by the PHY */
    LPC_CCU1->CLKCCU[CLK_USB1].CFG &= ~1;

   SetUsb1ClockPinmux ();

    /* switch to ulpi phy and turn on the power to phy*/
    // Clear PFSC (bit24) to prevent the port from forcing a high speed connection
    portsc = LPC_USB1->PORTSC1_D & 0x00FFFFFF;
    portsc |= _BIT(24); // force full speed connection OR
    //portsc &= ~_BIT(24); // clear PFSC to allow any speed connect
    portsc |= 0x80000000; // PTS select, bit 31:30, 0x2 = ULPI
    LPC_USB1->PORTSC1_D = portsc;

    /* reset the controller */
    LPC_USB1->USBCMD_D = _BIT(1);
    /* wait for reset to complete */
    while ((LPC_USB1->USBCMD_D & _BIT(1)));

    /* Program the controller to be the USB device mode */
    LPC_USB1->USBMODE_D =   0x02 | _BIT(3);
}

[lpcware]

Content originally posted in LPCWare by mc on Fri May 01 08:47:33 MST 2015
Hi toad,
Good to know that SMSC3343 is working. Cypress PHY may not be setting pull up correctly.

[lpcware]

Content originally posted in LPCWare by toad on Fri May 01 07:31:47 MST 2015
It seems that the Cypress PHY expects the device processor to monitor VBUS externally (not via the PHY) and use the external monitor to trigger the connection process.

http://www.cypress.com/?id=4&rID=42753

I am not sure that there is any way I could incorporate this model along side the ROM firmware so I have switched over to the SMSC 3343 which appears to be working

[stevebress]

Hi Toad,

Did you have to jump through any hoops to get the 3343 to work, or did it work as advertised? NXP has not been very helpful on this topic. Thanks!

[lpcware]

Content originally posted in LPCWare by mc on Thu Apr 30 17:20:00 MST 2015
Hi toad,
Could you please check whether you are getting reset interrupt in your code? Please place break point  at 
USBD_API->hw->ISR(hUsb) when USBSTS_URI bit is set?

---

Quote:
void USB1_IRQHandler(void)
{
  uint32_t disr = LPC_USB1->USBSTS_D;  

  if (disr & USBSTS_URI) {
USBD_API->hw->ISR(hUsb);
}
  else
  USBD_API->hw->ISR(hUsb);
}

---