Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, <SOME CLOCK INPUT>, true, false); |
/** * @brief CGU clock input list * These are possible input clocks for the CGU and can come * from both external (crystal) and internal (PLL) sources. These * clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T). */ typedef enum CHIP_CGU_CLKIN { CLKIN_32K,/*!< External 32KHz input */ CLKIN_IRC,/*!< Internal IRC (12MHz) input */ CLKIN_ENET_RX,/*!< External ENET_RX pin input */ CLKIN_ENET_TX,/*!< External ENET_TX pin input */ CLKIN_CLKIN,/*!< External GPCLKIN pin input */ CLKIN_RESERVED1, CLKIN_CRYSTAL,/*!< External (main) crystal pin input */ CLKIN_USBPLL,/*!< Internal USB PLL input */ CLKIN_AUDIOPLL,/*!< Internal Audio PLL input */ CLKIN_MAINPLL,/*!< Internal Main PLL input */ CLKIN_RESERVED2, CLKIN_RESERVED3, CLKIN_IDIVA,/*!< Internal divider A input */ CLKIN_IDIVB,/*!< Internal divider B input */ CLKIN_IDIVC,/*!< Internal divider C input */ CLKIN_IDIVD,/*!< Internal divider D input */ CLKIN_IDIVE,/*!< Internal divider E input */ CLKINPUT_PD/*!< External 32KHz input */ } CHIP_CGU_CLKIN_T; |
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 3); /* Setup divider A for main PLL rate divided by 3 */ Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVA, true, false); /* HSADC base clock = divider A input */ |
Chip_USB0_Init(); /* Sets USB PLL to 480Mhz */ Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_USBPLL, 6); /* Setup divider D for USB PLL rate divided by 6 */ Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVD, true, false); /* HSADC base clock = divider D input */ |
/* Select both positive and negative DC biasing for input 3 */ Chip_HSADC_SetACDCBias(LPC_ADCHS, 1, HSADC_CHANNEL_NODCBIAS, HSADC_CHANNEL_NODCBIAS); |
char countC[32} = ""; |
grep -r DMA ./ |grep -v \.h |cut -d':' -f 1|uniq |
./sct/sct_fsm.c ./source/capture_sgpio.c ./source/capture_vadc.c ./source/generator_sgpio.c ./source/main.c ./source/startup_LPC43xx.s ./uVision/Internal_SRAM/firmware.map ./uVision/Internal_SRAM/startup_lpc43xx.lst |