LPC2365 RX FIFO reset question

[isaotakashima]

I have problem that FIFO overrun error occur when start transmit/receive immediately after reset RX FIFO.

Here is questions.

1. What is the execution time of the RX FIFO reset?

2. How to confirm complete RX FIFO reset?

3. Is it when the RDR bit changes from 1 to 0?
  Or is the RX FIFO Reset bit automatically changed to 0?

Please reply as soon as possible.

Best regards,

Takashima

[Dezheng_Tang]

2. How to confirm complete RX FIFO reset?

As UM mentioned, RX FIFO Reset bit is self-clean, once you set this bit, poll this bit and wait until it goes to zero.

(3) Not just UART, any FIFO reset in the middle of the data communication will cause data corruption, overflow or underflow, frame error, timeout, etc. Some basic house keeping is needed before FIFO reset can happen, for the UART case, I would check the LSR first, wait until RBR is empty; even after FIFO reset is done, make sure it's "clean" in the LSR register. 

[CarlosCasillas]

Hi Isao,

In order to provide more details, could you please confirm if are you referring to the FIFO of the UART?

Have you already checked application note AN10689 “Full-duplex software UART for LPC2000”?

https://www.nxp.com/docs/en/application-note/AN10689.pdf

Hope this will be useful for you.
Best regards!
/Carlos

[isaotakashima]

Dear Carlos Casillas,

Thank you for your reply.

Unfortunately I cannot find out answer to my question from application note AN10689 “Full-duplex software UART for LPC2000”.

Please tell us which page describe RX FIFO reset phenomenon as soon as possible.

Best regards,

Takashima

[isaotakashima]

@CarlosCasillas

Could you please reply as soon as possible.

Our customer is waiting for your reply to solve this issue.

Best regards,

Takashima