Floating point denormalized numbers support on NXP M4f?

[lpcware]

Content originally posted in LPCWare by Kaveh.Firouzi on Fri Apr 10 11:22:51 MST 2015
Hello,

Does NXP M4f processors support denormalized numbers and operations?

Thanks in advance.

[lpcware]

Content originally posted in LPCWare by Kaveh.Firouzi on Mon Apr 13 06:04:43 MST 2015
You are right, the combination of using expf and setting FZ to zero worked. Thanks.

[lpcware]

Content originally posted in LPCWare by starblue on Mon Apr 13 02:36:51 MST 2015
Note that exp is the function for double, to use single precision you need expf.

You should also look at the generated assembly code, otherwise it is difficult to tell who is doing which part of the computation (the compiler, the software library or the hardware in the Cortex-M4F).

[lpcware]

Content originally posted in LPCWare by Kaveh.Firouzi on Sat Apr 11 17:37:10 MST 2015
Thanks. But I can't activate this mode. According to the datasheet setting the FZ bit in FPSCR to 0 should activate this mode, but it doesn't seem to work. Let me explain what happens:

As an example, I want to calculate a = exp(-100); which is 3.7201e-044 and is too small and needs to be denormalized. But I get zero. As I said, setting FZ to zero makes no difference. Although, when I did the following test:

float a;
a = exp(-100)*1e20;

I got the the correct result which is 3.72007594e-024! which means a is correctly computed and treated as a denormal number inside the FPU. So the problem happens when a is stored back to memory as zero.

Could you pleas let me know how to fix this?

Regards

[lpcware]

Content originally posted in LPCWare by nerd herd on Fri Apr 10 13:47:34 MST 2015
Hi Kaveh.Firouzi,

To answer your question, here is an excerpt from TheFallGuy's link:

Floating Point Unit (FPU) in the Cortex-M4F processor providing:
— 32-bit instructions for single-precision (C float) data-processing operations.
— Combined Multiply and Accumulate instructions for increased precision (Fused
MAC).
— Hardware support for conversion, addition, subtraction, multiplication with
optional accumulate, division, and square-root.
— Hardware support for denormals and all IEEE rounding modes.
— 32 dedicated 32-bit single precision registers, also addressable as 16 double-word
registers.
— Decoupled three stage pipeline.

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Fri Apr 10 12:28:47 MST 2015
The NXP Cortex-m4f is the same as everybody else's, and is described in the ARM documentation:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf