Fri Mar 28, 2014 09:41:49: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\NXP\Trace_LPC18xx_LPC43xx.dmac Fri Mar 28, 2014 09:41:49: JLINK command: ProjectFile = C:\My Project\IAR\settings\ProjM0_Flash.jlink, return = 0 Fri Mar 28, 2014 09:41:49: JLINK command: scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\NXP\LPC4350_DebugCortexM0.JLinkScript, return = 0 Fri Mar 28, 2014 09:41:49: Device "LPC4357_M0" selected (0 KB flash, 0 KB RAM). Fri Mar 28, 2014 09:41:49: DLL version: V4.82 Fri Mar 28, 2014 09:41:49: Firmware: J-Link V9 compiled Mar 10 2014 19:02:08 Fri Mar 28, 2014 09:41:49: JTAG speed is initially set to: 32 kHz Fri Mar 28, 2014 09:41:49: TotalIRLen = 8, IRPrint = 0x0011 Fri Mar 28, 2014 09:41:49: TotalIRLen = 8, IRPrint = 0x0011 Fri Mar 28, 2014 09:41:49: Found Cortex-M0 r0p0, Little endian. Fri Mar 28, 2014 09:41:49: FPUnit: 2 code (BP) slots and 0 literal slots Fri Mar 28, 2014 09:41:49: LPC43xx Cortex-M0 (reset): Performing core reset for Cortex-M0 co-processor. No other reset types available for this core. Fri Mar 28, 2014 09:41:50: J-Link script: Performing reset sequence Fri Mar 28, 2014 09:41:50: Hardware reset with strategy 1 was performed Fri Mar 28, 2014 09:41:50: Initial reset was performed Fri Mar 28, 2014 09:41:50: Found 2 JTAG devices, Total IRLen = 8: Fri Mar 28, 2014 09:41:50: #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP Fri Mar 28, 2014 09:41:50: #1 Id: 0x0BA01477, IRLen: 4, IRPrint: 0x1 CoreSight SW-DP Fri Mar 28, 2014 09:41:50: 1912 bytes downloaded and verified (13.34 Kbytes/sec) Fri Mar 28, 2014 09:41:50: Warning: Verify error at address 0x1B000000, target byte: 0xFF, byte in file: 0x18 Fri Mar 28, 2014 09:41:50: Warning: Verify error at address 0x1B000001, target byte: 0xFF, byte in file: 0x04 ... ... Fri Mar 28, 2014 09:41:50: Warning: Verify error at address 0x1B0000C8, target byte: 0xFF, byte in file: 0xB1 Fri Mar 28, 2014 09:41:50: Warning: Too many verify errors, only the first 200 are displayed Fri Mar 28, 2014 09:41:52: Warning: There were warnings during download, see Log Window Fri Mar 28, 2014 09:41:52: Loaded debugee: C:\My Project\IAR\Flash\Exe\ProjM0.out Fri Mar 28, 2014 09:41:52: LPC43xx Cortex-M0 (reset): Performing core reset for Cortex-M0 co-processor. No other reset types available for this core. Fri Mar 28, 2014 09:41:52: J-Link script: Performing reset sequence Fri Mar 28, 2014 09:41:52: Software reset was performed Fri Mar 28, 2014 09:41:52: Warning: Stack pointer is setup to incorrect alignment. Stack addr = 0xFFFFFFFF Fri Mar 28, 2014 09:41:52: Target reset Fri Mar 28, 2014 09:41:53: There were 2 warnings during the initialization of the debugging session. |
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x1B000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x1B0000C0; define symbol __ICFEDIT_region_ROM_end__ = 0x1B07FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x10080000; define symbol __ICFEDIT_region_RAM_end__ = 0x10087FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x200; /**** End of ICF editor section. ###ICF###*/ /********** Core Shared - AHB SRAM Region 1 **********/ define symbol SHARED_RAM_start__ = 0x20007FE0; define symbol SHARED_RAM_end__ = 0x20007FFF; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define region SHARED_RAM_region = mem:[from SHARED_RAM_start__ to SHARED_RAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place at start of SHARED_RAM_region { section .shared_data }; |
IPC_haltSlave(); IPC_masterInitInterrupt(masterInterruptCallback); IPC_startSlave(); while(intFlag != MSG_PENDING) __WFE(); IPC_resetIntFlag(); |
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x1B000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x1B000114; define symbol __ICFEDIT_region_ROM_end__ = 0x1B07FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x10080000; define symbol __ICFEDIT_region_RAM_end__ = 0x10087FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_heap__ = 0x200; /**** End of ICF editor section. ###ICF###*/ define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; |
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x1A000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x1A000114; define symbol __ICFEDIT_region_ROM_end__ = 0x1A07FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; define symbol __ICFEDIT_region_RAM_end__ = 0x10007FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x2000; define symbol __ICFEDIT_size_heap__ = 0x4000; /**** End of ICF editor section. ###ICF###*/ /********** Flash BankB Region **********/ define symbol __ICFEDIT_region_ROM_BANKB_start__ = 0x1B000000; define symbol __ICFEDIT_region_ROM_BANKB_end__ = 0x1B07FFFF; /********** Local SRAM Region **********/ define symbol LOCAL_SRAM_start__ = 0x10080000; define symbol LOCAL_SRAM_end__ = 0x10089FFF; /********** AHB SRAM Region 1 **********/ define symbol AHB_SRAM1_start__ = 0x20000000; define symbol AHB_SRAM1_end__ = 0x20007FFF; /********** AHB SRAM Region 2 **********/ define symbol AHB_SRAM2_start__ = 0x20008000; define symbol AHB_SRAM2_end__ = 0x2000BFFF; /********* ETB/AHB SRAM Region *********/ define symbol ETB_SRAM_start__ = 0x2000C000; define symbol ETB_SRAM_end__ = 0x2000FFFF; /********* CRP REGION *********/ define symbol __CRP_start__ = 0x1A0002FC; define symbol __CRP_end__ = 0x1A0002FF; /********* EEPROM REGION *********/ define symbol __EE_start__ = 0x20040000; define symbol __EE_end__ = 0x20044000; /********* External RAM REGION - SDRAM 1 *********/ define symbol _EXT_RAM_start__ = 0x28000000; define symbol _EXT_RAM_end__ = 0x283FFFFF; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; define region ROM_BANKB_region = mem:[from __ICFEDIT_region_ROM_BANKB_start__ to __ICFEDIT_region_ROM_BANKB_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define region LOCAL_SRAM_region = mem:[from LOCAL_SRAM_start__ to LOCAL_SRAM_end__]; define region AHB_SRAM1_region = mem:[from AHB_SRAM1_start__ to AHB_SRAM1_end__]; define region AHB_SRAM2_region = mem:[from AHB_SRAM2_start__ to AHB_SRAM2_end__]; define region ETB_SRAM_region = mem:[from ETB_SRAM_start__ to ETB_SRAM_end__]; define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; define region EEPROM_region = mem:[from __EE_start__ to __EE_end__]; define region EXT_RAM_region = mem:[from _EXT_RAM_start__ to _EXT_RAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; do not initialize { section .eeprom }; place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; place in LOCAL_SRAM_region { section .local_sram }; place at end of AHB_SRAM1_region { section .shared_data}; place in AHB_SRAM1_region { section .ahb_sram1 }; place in AHB_SRAM2_region { section .ahb_sram2 }; place in ETB_SRAM_region { section .etb_sram }; place in EEPROM_region { section .eeprom }; place at start of ROM_BANKB_region { section .M0_CODE }; place in CRP_region { section .crp }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP }; place in EXT_RAM_region { section GUI_RAM }; |