Are LPC182x devices subject to C_CAN errata ?

[lpcware]

Content originally posted in LPCWare by devlin on Wed Oct 01 13:23:53 MST 2014
Hi,
We're planning on using the LPC1822JET100 device in a new project.
We would like to use 2x CAN, AD-converter and 2x I2C bus at the same time.

When reading the errata sheet (rev 5 / 15 Aug 2014) we are a little bit confused  regarding C_CAN.1 problem.

The errata says in 3.1:
"On the LPC185x flash-based devices, there is an issue with the C_CAN controller ...."

Does this mean that the LPC182x devices are NOT affected ?
Or,  should the errata be read as 'On the LPC185x/3x/2x/1x flash-based devices ....' ?

In the Users manual it seems to be a generic problem for all 18xx devices (which makes more sense)
From section 42.2:
Remark: Use of C_CAN controller excludes operation of all other peripherals connected
to the same bus bridge. See the LPC18xx errata.

Any input is welcome as we may need to skip one CAN-bus or use some other device.

Thanks
/devlin

[lpcware]

Content originally posted in LPCWare by devlin on Thu Feb 11 01:58:42 MST 2016
We have now solved the CAN and I2C problem with the above RevA cpu.

The problem was that we first initialized the CAN-device and the disabled it,
when we disabled CAN we also powered off the CAN-clock.
When we initialized I2C and tried to read current clock-speed it hanged the CPU -
that is because I2C clock is a part of the CAN clock-tree which was disabled.

Not disabling the CAN-clock solved our problem.

/devlin

[lpcware]

Content originally posted in LPCWare by devlin on Mon Nov 30 04:09:17 MST 2015
Hi, I'm afraid this is a very late followup...

We have now been able to get hold of some 'supposedly' Rev A chips, unfortunately
these chip still seems to have C_CAN.1 and IBAT.1 errata problems.

We would like to use AD,I2C and both CAN busses,
using AD+I2C works fine
using 2x CAN busses (without AD/I2C) works fine.
using AD+I2C+CAN hangs in init or short after.

We get a hanged CPU in the following situations (we loose JTAG connection etc.)
1) I2C is initiated before CAN.
  Hangs in Chip_ADC_EnableChannel() (in adc_18xx_43xx.c, line 237)
 

    pADC->CR |= ADC_CR_CH_SEL(channel);

  i.e init is completed, crash on first AD-conversion.

2) CAN is initiated before I2C
   Hangs in Chip_Clock_GetRate() (clock_18xx_43xx.c, line 684 or 688)

    reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG;

Both of these hangs looks like the problem described in C_CAN.1 errata, but this problem
should be gone in rev A !

With IBAT.1 we're using a uCap connected to VBAT. Without the workaround from the errata we
get 30min running time in the RTC, with workaround we get 6h.
This is similar on both rev '-' and rev 'A' chips.

Chip markings are:

LPC1822JET100
P1XN24.00   17
ESD15020A

According to our supplier the above should be a Rev 'A', but I think our tests show something else.
Is there some configuration bit or something you could read from the CPU to be sure it is a rev 'A' chip ?

Regards
Devlin

[lpcware]

Content originally posted in LPCWare by Feo Elektronik WR on Tue May 12 09:22:58 MST 2015
Are there any plans to fix C_CAN1.1 also for flashless parts, specifically LPC1850 aund LPC4350?

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Oct 06 03:01:53 MST 2014
Hello,

the CAN problem affects all the current derivatives of the LPC1800, so also the type you plan to use.

But there is a solution right ahead: we fixed this problem in a new silicon version (flash based) which will be released this quarter.
So if you can work around this problem somehow for the first weeks of your development, then you can decide for the LPC182x without headache.

Please contact your distributor for the availability of the Rev A of the silicon with internal flash (current version is Rev "-").

Regards,
NXP Support Team