Hello Gloria,
The FRDM-K64F contains an external reference of 50 MHz provided by the Ethernet Phy which is used to feed the MCU. As you can see in the image below it is divided by a factor which usually is configured as PRDIV = 0x13 to divide the external reference clock by a factor of 20 to feed the PLL with a 2.5 MHz signal. The PLL internally multiplies the frequency by a factor defined by VDIV0 which usually is configured as 0x18 to multiply by a factor of 48 to get 120 MHz. Since you want a 100 MHz output you need to modify this factor to 40 to get that frequency so you need to configure VDIV0 = 0x10.
So, what you need to do is to change that value in the KSDK configurations. In the file board.c is defined an structure called clock_manager_user_config_t g_defaultClockConfigRun which contains these configurations.
const clock_manager_user_config_t g_defaultClockConfigRun =
{
.mcgConfig =
{
.mcg_mode = kMcgModePEE, // Work in PEE mode.
.irclkEnable = true, // MCGIRCLK enable.
.irclkEnableInStop = false, // MCGIRCLK disable in STOP mode.
.ircs = kMcgIrcSlow, // Select IRC32k.
.fcrdiv = 0U, // FCRDIV is 0.
.frdiv = 7U,
.drs = kMcgDcoRangeSelLow, // Low frequency range
.dmx32 = kMcgDmx32Default, // DCO has a default range of 25%
.oscsel = kMcgOscselOsc, // Select OSC
.pll0EnableInFllMode = false, // PLL0 disable
.pll0EnableInStop = false, // PLL0 disalbe in STOP mode
.prdiv0 = 0x13U,
.vdiv0 = 0x18U,
},
.simConfig =
{
.pllFllSel = kClockPllFllSelPll, // PLLFLLSEL select PLL.
.er32kSrc = kClockEr32kSrcRtc, // ERCLK32K selection, use RTC.
.outdiv1 = 0U,
.outdiv2 = 1U,
.outdiv3 = 1U,
.outdiv4 = 4U,
},
.oscerConfig =
{
.enable = true, // OSCERCLK enable.
.enableInStop = false, // OSCERCLK disable in STOP mode.
}
};
Change the value for the field vdiv to 0x10 and you will obtain a 100 MHz core clock.
Best regards,
Earl.
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Hello Gloria,
The FRDM-K64F contains an external reference of 50 MHz provided by the Ethernet Phy which is used to feed the MCU. As you can see in the image below it is divided by a factor which usually is configured as PRDIV = 0x13 to divide the external reference clock by a factor of 20 to feed the PLL with a 2.5 MHz signal. The PLL internally multiplies the frequency by a factor defined by VDIV0 which usually is configured as 0x18 to multiply by a factor of 48 to get 120 MHz. Since you want a 100 MHz output you need to modify this factor to 40 to get that frequency so you need to configure VDIV0 = 0x10.
So, what you need to do is to change that value in the KSDK configurations. In the file board.c is defined an structure called clock_manager_user_config_t g_defaultClockConfigRun which contains these configurations.
const clock_manager_user_config_t g_defaultClockConfigRun =
{
.mcgConfig =
{
.mcg_mode = kMcgModePEE, // Work in PEE mode.
.irclkEnable = true, // MCGIRCLK enable.
.irclkEnableInStop = false, // MCGIRCLK disable in STOP mode.
.ircs = kMcgIrcSlow, // Select IRC32k.
.fcrdiv = 0U, // FCRDIV is 0.
.frdiv = 7U,
.drs = kMcgDcoRangeSelLow, // Low frequency range
.dmx32 = kMcgDmx32Default, // DCO has a default range of 25%
.oscsel = kMcgOscselOsc, // Select OSC
.pll0EnableInFllMode = false, // PLL0 disable
.pll0EnableInStop = false, // PLL0 disalbe in STOP mode
.prdiv0 = 0x13U,
.vdiv0 = 0x18U,
},
.simConfig =
{
.pllFllSel = kClockPllFllSelPll, // PLLFLLSEL select PLL.
.er32kSrc = kClockEr32kSrcRtc, // ERCLK32K selection, use RTC.
.outdiv1 = 0U,
.outdiv2 = 1U,
.outdiv3 = 1U,
.outdiv4 = 4U,
},
.oscerConfig =
{
.enable = true, // OSCERCLK enable.
.enableInStop = false, // OSCERCLK disable in STOP mode.
}
};
Change the value for the field vdiv to 0x10 and you will obtain a 100 MHz core clock.
Best regards,
Earl.
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