Why are there ADC clock frequency minimum operating conditions?

[danebouchie]

On the K10 datasheet (specifically the MK10DX128VLK7) the 16-bit minimum clock frequency is different then the <= 13 bit clock frequency:

fADCK ADC conversion clock frequency ≤ 13-bit mode: 1.0 — 18.0 MHz
fADCK ADC conversion clock frequency 16-bit mode: 2.0 — 12.0 MHz

Why is that? Why do are there minimum limits to the ADC frequency? And what happens if a clock frequency is used that is below this frequency? 

I noticed this warning in Processor Expert when I was using a 1 MHz ADC frequency in 16-bit mode, but the clock configuration was a valid configuration other than this warning, and from what I can tell, it seemed to work fine. I need to know if this is critical to ADC functionality.

[Alexis_A]

Hello @danebouchie,

The ADC module works with a minimum and maximum sample rate and this is to ensure the proper functionality of the module. Any value outside the specification, the proper behavior of the module is not guaranteed. 

Best Regards,

Alexis Andalon