MK10F12 access violation at 0x4005200E - 0x40064011 read and write

[mrandreas]

     I'm getting error 65: access violation at 0x40064xxx : no 'write' permission and also some read violation aswel in the : SystemInit (void)

     WDOG, SIM, PORTA and MGC definitions access violation.

     I'm also getting HardFault_Handler error.

     I'm using the chip: MK10FN1M0VLQ12

     Anny Ideas?

best regards

Andreas

[chris_brown]

Andreas,

Which IDE are you using?

Also, if you are getting a hard fault error when writing to MCG registers the most likely cause is that you are mis-configuring the MCG.  Examples might include:

• Configuring MCGOUTCLK to too high of a frequency before modifying clock dividers (OUTDIV1 - 4).  Doing this might over clock your flash clock and cause your program to fail. 
• Configuring the PLL input frequency to an invalid value.  For the part you are using, this reference frequency must be in the range of 8-16 MHz (as per the reference manual, Table 25-23. MCGOUTCLK Frequency Calculation Options). 

What command is causing this hard fault and what are the 5 lines of code before this command?

Hope this helps,

Chris

[mrandreas]

I'm using Keil with unmodified startup_MK10F12.s, system_MK10F12.c and the MK10F12.h for this chip (MK10FN1M0VLQ12).

I've been developing on the K60 tower evaluation board and ported this project to the target (MK10FN1M0VLQ12) and I've testing a hello world project that doesn't do anything.

In the simple helloworld project I’m getting the access violation fault while in the ported project I’m only getting hard fault. I’ve also commented out everything in the ported project (only using startup..m system… and mk10f12.h), but I’m not getting the access violation faults.

> 5 lines of code before this command?

The call stack doesn’t give me any clue. I don’t know.

I'm using the following clock setup.

   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode

Reference clock source for MCG module is the slow internal clock source 32.768kHz

         Core clock = 41.94MHz, BusClock = 41.94MHz

#if (CLOCK_SETUP == 0)

#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */

#define CPU_XTAL1_CLK_HZ 8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */

#define CPU_XTAL32k_CLK_HZ 32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */

#define CPU_INT_SLOW_CLK_HZ 32768u    /* Value of the slow internal oscillator clock frequency in Hz  */

#define CPU_INT_FAST_CLK_HZ 4000000u  /* Value of the fast internal oscillator clock frequency in Hz */

#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */

When debugging, the first issue is when reading and writing to the watchdog:

WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */

WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */

[anthony_huereca]

Hi,

  I noticed by searching for your other threads that you were using the TWR-K60N512 board. There's a lot of significant differences in the clock module between the 1.x 100MHz Kinetis part on that board, and the 120MHz Kinetis part you're trying to port to. This is very likely what is causing the problems. Please see this app note which covers the differences: http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4526.pdf

  Also take a look at this thread for a full explanation of how all the chips are related Re: Additional Pin mux functions - which silicon revisions did they start?

  You might also want to use the TWR-K70F120M sample code to start your code base, which will implement those changes on your K10F part: https://www.freescale.com/webapp/Download?colCode=KINETIS_120MHZ_SC

  Finally if that isn't the problem, double check your VBAT connection. An access to the RTC if VBAT isn't connected to power will result in problems as well.

Hope that helps!

-Anthony

[mrandreas]

Hi,

The target with an MK10FN1M0VLQ12 uses an 25Mhz osc to XTAL0 and EXTAL0. However it should be possible to only use the internal clock.

When using the internal clock (Config below) I get the following issues:

1) cannot access memory -

(according to keil - issues with debug pwr or debug clock frequency) What other things that could cause this?

2) When writing to UART1 BLD, C2 or any of the other UART1 registers, the program goes to HARD Fault handler.

Could this be related to clock settings? Any Ideas what could be causing this?

best regards

Andreas

/* SIM_SCGC5: PORTA=1 */

  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */

  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */

  /* SIM_SOPT2: PLLFLLSEL=0 */

  SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */

  /* SIM_SOPT1: OSC32KSEL=0 */

  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */

  /* SIM_SCGC1: OSC1=1 */

  SIM->SCGC1 |= (uint32_t)0x20UL;

  /* PORTA_PCR18: ISF=0,MUX=0 */

  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;

  /* Switch to FEI Mode */

  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */

  MCG->C1 = (uint8_t)0x06U;

  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */

  MCG->C2 = (uint8_t)0x20U;

  /* MCG_C4: DMX32=0,DRST_DRS=1 */

  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);

  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  OSC0->CR = (uint8_t)0x80U;

  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  OSC1->CR = (uint8_t)0x80U;

  /* MCG_C7: OSCSEL=0 */

  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;

  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */

  MCG->C5 = (uint8_t)0x00U;

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */

  MCG->C6 = (uint8_t)0x00U;             /* 3 */

  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */

  MCG->C11 = (uint8_t)0x00U;            /* 3 */

  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */

  MCG->C12 = (uint8_t)0x00U;            /* 3 */

[chris_brown]

Have you ever only tried stepping through the watchdog init code?  Because you cannot step through this code.  Can you set a breakpoint  at some point after the watchdog has been disabled and run to this breakpoint?  If you are using the unmodified KEIL startup files you should be able to make it past these points.  Let me know if that helps.