MK10 MCG Clock Configuration

[briancook]

I am migrating from an MK40 to an MK10 part and am having issues configuring the PLL correctly (I do know about the 2x frequency going into the FLL. My board has an 8MHz osc (OSC0) and I want to program a 96MHz MCGOutClk.  To generate this, I have used the following settings:

C1: FRDIV=3, CLKS=2

C2: ANGE0=1, HGO0=1 EREFS0=1

C5: PRDIV0=0

C6: VDIV0=8, PLLS=1

When I set these parameters, using VDIV=8, the code generates a hardware fault.  If I set VDIV=7, the code runs, but I end with McgOutClk=92MHz, which isn't what I want.  My code is including MK10F12.h from KDS SDK 1.3.0.  I've hardcoded the values to make the code easier to read.  The part that is on the board is a MK10FN1M0VMD12.

Original Attachment has been moved to: bsp_interface.cpp.zip

[briancook]

I have resolved my issues.  The hardware fault was caused by the flash clock frequency being too high (32MHz).

These are my final values to produce McgOutClk of 96MHz for an 8MHz osc.

MCG_C1: FRDIV=3, CLKS=2

MCGC2: RANGE0=2, HGO0=1 EREFS0=1

MCGC5: PRDIV0=0

MCGC6: VDIV0=8, PLLS=1

SIM_CLKDIV1_OUTDIV1 = 0

SIM_CLKDIV1_OUTDIV2 = 1

SIM_CLKDIV1_OUTDIV3 = 1

SIM_CLKDIV1_OUTDIV4 = 3

[jeremyzhou]

Hi Brian,

I'm glad to hear that you solved the issue.

If you have any other questions, please just feel free to contact with me.
Have a great day,
Ping

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[briancook]

I have not yet been able to program the K10FN for an McgOutClk of 96MHz.  I think the issue is related to the MCG differences between the "100MHz" and "120MHz" MCUs.  AppNote  AN4526 talks about this in the MCG section.  The "120MHz" MCU can support a PLL reference range between 8-16MHz.  Does my external osc need to be greater than 8MHz to achieve an McgClkOut of 96MHz (or higher)?  The MCG example in the K10P144M120SF3RM shows how to achieve a 120MHz McgOutClk with a 16MHz osc.  Can 120MHz be achieved with an 8MHz osc?

[briancook]

I implemented your code above.  Unless I'm missing something, the code above generates an McgOutClk of 48Mhz for an external 8MHz osc.  I verified this by calculating McOutClk = ((8MHz / PRDIV) * VDIV)/2.  I then used the calcaluted 48MHz to program my OS systick interrupt and UART baudrates, which work as expected (systick interrupt every 1ms, baudrate functional at 115200). 

[jeremyzhou]

Hi

Please checking the complete code.

void __init_hardware(void)
{
  /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
  /*** ### MK10FN1M0VMD12 "Cpu" init code ... ***/
  /* Disable the WDOG module */
  /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
  WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
  /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
  WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
  /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKsrc=1,WDOGEN=0 */
  WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
                 WDOG_STCTRLH_WAITEN_MASK |
                 WDOG_STCTRLH_STOPEN_MASK |
                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
                 WDOG_STCTRLH_CLKSRC_MASK |
                 0x0100U;
  /* System clock initialization */
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                SIM_CLKDIV1_OUTDIV2(0x01) |
                SIM_CLKDIV1_OUTDIV3(0x03) |
                SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
  /* SIM_SCGC5: PORTA=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
  if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
    /* PMC_REGSC: ACKISO=1 */
    PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
  }
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                SIM_CLKDIV1_OUTDIV2(0x01) |
                SIM_CLKDIV1_OUTDIV3(0x01) |
                SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
  /* SIM_SOPT2: PLLFLLSEL=0 */
  SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL(0x03)); /* Select FLL as a clock source for various peripherals */
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL_MASK); /* System oscillator drives 32 kHz clock for various peripherals */
  /* SIM_SCGC1: OSC1=1 */
  SIM_SCGC1 |= SIM_SCGC1_OSC1_MASK;
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* PORTA_PCR19: ISF=0,MUX=0 */
  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* Switch to FBE Mode */
  /* MCG_C7: OSCSEL=0 */
  MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
  /* MCG_C10: LOCRE2=0,??=0,RANGE1=0,HGO1=0,EREFS1=0,??=0,??=0 */
  MCG_C10 = MCG_C10_RANGE1(0x00);
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
  MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=1 */
  OSC0_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK);
  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC1_CR = OSC_CR_ERCLKEN_MASK;
  /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=1 */
  MCG_C5 = MCG_C5_PRDIV0(0x01);
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
  MCG_C6 = MCG_C6_VDIV0(0x08);
  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
  MCG_C11 = MCG_C11_PRDIV1(0x00);
  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
  MCG_C12 = MCG_C12_VDIV1(0x00);
  while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
  }
  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  /* Switch to PBE Mode */
  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
  MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x08));
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
  }
  /* Switch to PEE Mode */
  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
  }
  /*** End of PE initialization code after reset ***/
  /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}

Have a great day,
Ping

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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[briancook]

Hello Ping,

The configuration that you listed does not work for the K10.  The code gets hung in the MCG_S_PLLST loop check.  By setting MCG_C5 PLLS to 0 explains why this is happening.  Your configuration suggests that you want me to configure the MCG for FEE mode.  If this is the case, MCG_C4 needs to be configured instead of MCG_C5.  If I set PLLS to 1 to configure the PLL for PEE mode, I get half the frequency (48MHz) for McgOutClk (as discussed above).  Can you provided me with all register settings needed to achieve 96MHz?

[briancook]

Yes, this may be the issue.  However, I want to achieve an McgOutClk of 96MHz.  If I divide the freq to 4MHz (PRDIV=1), I'm not able to achieve my freq because the largest value of VDIV0 is 47.  This generates an McgOutClk of 92MHz ((4*47)/2).  How can I increase the frequency?  The reference manual (K10P144M120SF3RM) shows an example at 25.5.3.1 where a 16MHz osc is divided to 8MHz by PRDIV in order to achieve 120MHz McgOutClk.  That is why I thought 8MHz would be workable.

[jeremyzhou]

Hi Brian,

Thanks for your reply.

Please try the kind of configurations below to work it out.

  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                SIM_CLKDIV1_OUTDIV2(0x01) |
                SIM_CLKDIV1_OUTDIV3(0x01) |
                SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=1 */
  MCG_C5 = MCG_C5_PRDIV0(0x01);
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
  MCG_C6 = MCG_C6_VDIV0(0x08);      // MCGOUTCLK= (8/2)*24, Core/system clocks=96 MHz, Bus clock=48MHz; Flexbus clock=48 MHz; Flash clock= 24 MHz

Have a great day,
Ping

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[jeremyzhou]

Hi Brain,

After had a brief look through the code, I didn't find any wrong except the MCG_C5[PRDIV0] setting.

Regarding to the PRDIV0 bits setting, the resulting frequency must be in the range of 2 MHz to 4 MHz, however I found that MCG_C5[PRDIV0]=0 in your code, in another word, the 8 MHz beyond the range.

	tempReg = MCG_C5;	// Configure MCG_C5
	tempReg &= ~MCG_C5_PRDIV0_MASK;	// If the PLL is to run in STOP mode then the PLLSTEN bit needs to be OR'ed in here or in user code
	tempReg |= MCG_C5_PRDIV0(0);	// Set the PRDIV field to generate an 8MHz reference clock
	MCG_C5 = tempReg;

Have a great day,
Ping

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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