Kinetis KE18 DMA doesn't rewind source address if destination is ADC

[pablo_slavkin]

I'm playing with ADC and DMA and I'd configure a DMA channel to copy ram->ram without problem, and after the citter reaches zero it generates IRQ and the source address and destination address rewind using SLAST and DLAST, it all goes fine, BUT if the destination is ADC->SC1[0] (to begin a ADC sample) the ADC begins normally and DMA does his work fine, but after CITER reaches zero, DMA doesn't rewind nor generate IRQ. The only single change was the destinatino adress. Of course in that case the destination address don't move becouse always point to same ADC2->SC1[0].

   here is the TCD I'm using

9    DMA0->TCD[0].CSR&=~0x0080;
8 DMA0->TCD[0].SADDR=(uint32_t)Adc_Sc;      //Adc_Sc is an 8 byte arrays filled with 0x07
7 DMA0->TCD[0].SOFF=1;
6 DMA0->TCD[0].ATTR=0x0000;
5 DMA0->TCD[0].NBYTES_MLNO=1;
4 DMA0->TCD[0].SLAST=-8;                                          //when Citer reaches zero Adc_Sc doesn't rewind!! 
3 DMA0->TCD[0].DADDR=(uint32_t)&ADC2->SC1[0];    //if I change these with any ram pos, all goes fine

2 DMA0->TCD[0].DOFF=0;
1 DMA0->TCD[0].DLAST_SGA=0;
48 DMA0->TCD[0].CSR=0x0002;                           //when Citer reaches zero it does not generate irq
1 DMA0->TCD[0].CITER_ELINKYES=8;               //using debug I've checked it reaches zero normally
2 DMA0->TCD[0].BITER_ELINKYES=8;
3 DMA0->SERQ=0x00;
4

[pablo_slavkin]

Hi Mark, thanks for your answer, You're right, there was an error shining on the register.. So after a couple of test I found that ADC2->SC1[0] is of 32bits long, and it's seems he does'n like that the DMA write to it like a 8bit regs. So I change the DMA->ATRR from 8 to 32 bits access and work like a charm... It seems strange, cose I've saw some examples with 8 bits access to that reg from the DMA.. in anyway, now it's working. The irq jump and the address of source get rewind, and error register in Zero.

Thanks and  keep rocking!

There it's my new TCD

10DMA0->TCD[0].SADDR=(uint32_t)&Adc_Sc[0];   //now Adc_Sc is a 8x32 bits array 
9 DMA0->TCD[0].SOFF=4;//
8 DMA0->TCD[0].ATTR=0x0202;//32 bits acces from source and dest
7 DMA0->TCD[0].NBYTES_MLNO=4;
6 DMA0->TCD[0].SLAST=-32;// yes, now it is used to restor SADDR
5 DMA0->TCD[0].DADDR=(uint32_t)&ADC2->SC1[0];    //hey! took your 32 bits! 24 all zeroes...
4 DMA0->TCD[0].DOFF=0;
3 DMA0->TCD[0].DLAST_SGA=0;//
2 DMA0->TCD[0].CSR=0x0002;                              //irq jump after 8 access
1 DMA0->TCD[0].CITER_ELINKNO=8;
51 DMA0->TCD[0].BITER_ELINKNO=8;
1 DMA0->CINT=0;

[mjbcswitzerland]

Pablo

Check the DMA error register.

If it is signaling an error (it will specify the DMA channel and whether it was due to source and destination) it will also cause the DMA cycle to be aborted and so stop it from completing its operation.

Regards

Mark