Hello,
Not really, the register programming is independent of OS used or in a bare metal, but it can vary where the register setup is done (PLL, DIVISORS,…etc).
You need to have a look at the LCDC Pixel clock chain:

Most probably your solution is using PLL0 output (SIM_SOPT2) and then going to SIM_CLKDIV3 and then LCDC_LPCR_PCD
So, check what is your PLL0/PLL1 output frequency and calculate LCDCFRAC/LCDCDIV for your required pixel clock.
Check D4DLCDHW_Init_K70LCDC_TwrRgbB(void) function.
LCDC_LPCR_PCD(D4DLCDHWFB_PANEL_CLKDIV); //Divide 120 PLL clock by (12+1)=13 to get 9.23MHz clock
And for your display, I am not sure if you need to specify the Vertical and blanking periods back porch, front porch,..etc. You will have to check the display datasheet.
Luis