K70 + Display without VSYNC & HSYNC

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K70 + Display without VSYNC & HSYNC

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joelesco
Contributor III

Hi !

I would like to plug with the Kinetis K70 a display (Winstar WF43G)  wich do not have VSYNC and HSYNC ! It only need the pixel clock. I'm using the D4D with CW. I would like to modify the low_level_drivers.

I was trying first my code with the TWR-LCD-RGB .  The frequency typ. of the LCD CLOCK was  10.87 Mhz, now I would like to change it to 9Mhz.

If someone can guide me for this manipulation would be very nice !!!!!!!!!!


Thanks a lot

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LuisCasado
NXP Employee
NXP Employee

Hello,

Not really, the register programming is independent of OS used  or in a bare metal, but it can vary where the register setup is done (PLL, DIVISORS,…etc).

You need to have a look at the LCDC Pixel clock chain:

Most probably your solution is using PLL0 output (SIM_SOPT2) and then going to SIM_CLKDIV3 and then LCDC_LPCR_PCD

So, check what is your PLL0/PLL1 output frequency and calculate LCDCFRAC/LCDCDIV for your required pixel clock.

Check D4DLCDHW_Init_K70LCDC_TwrRgbB(void) function.

LCDC_LPCR_PCD(D4DLCDHWFB_PANEL_CLKDIV);             //Divide 120 PLL clock by (12+1)=13 to get 9.23MHz clock

And for your display, I am not sure if you need to specify the Vertical and blanking periods back porch, front porch,..etc. You will have to check the display datasheet.

Luis

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LuisCasado
NXP Employee
NXP Employee

Hello,

Are you using MQX?

Regards,

Luis

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joelesco
Contributor III

Hello Luis,

For the moment i'm using Baremetal only. Does that change something ?

Thanks !

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LuisCasado
NXP Employee
NXP Employee

Hello,

Not really, the register programming is independent of OS used  or in a bare metal, but it can vary where the register setup is done (PLL, DIVISORS,…etc).

You need to have a look at the LCDC Pixel clock chain:

Most probably your solution is using PLL0 output (SIM_SOPT2) and then going to SIM_CLKDIV3 and then LCDC_LPCR_PCD

So, check what is your PLL0/PLL1 output frequency and calculate LCDCFRAC/LCDCDIV for your required pixel clock.

Check D4DLCDHW_Init_K70LCDC_TwrRgbB(void) function.

LCDC_LPCR_PCD(D4DLCDHWFB_PANEL_CLKDIV);             //Divide 120 PLL clock by (12+1)=13 to get 9.23MHz clock

And for your display, I am not sure if you need to specify the Vertical and blanking periods back porch, front porch,..etc. You will have to check the display datasheet.

Luis

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joelesco
Contributor III

Thanks a lot Luis for your help and all the details  !

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