Hi,
I have been wondering if it would be possible to use only the upper half of the AD bus to drive external asynchronous SRAM on Kinetis K60? I would like to connect lines AD[31:16] to SRAM A[0:15] through a latch and the same AD[31:16] to SRAM DATA[0:15].
I know it is possible to use the lower half of the bus to achieve it, but unfortunately AD[0:15] on this MCU conflicts with many other interesting peripherals on PORTC, so I would like to use the upper half.
The RM states:
• Address lines : FB_AD from FB_AD0 upward
• Data lines
• If CSCR[BLS] = 0, FB_AD from FB_AD31 downward
• If CSCR[BLS] = 1, FB_AD from FB_AD0 upward
But then it states:
• The address is driven on the full FB_AD[31:8] bus in the first clock.
• The device tristates FB_AD[31:16] on the second clock and continues to drive
address on FB_AD[15:0] throughout the bus cycle.
• The external device returns the read data on FB_AD[31:16] and may tristate the data
line or continue driving the data one clock after FB_TA is sampled asserted.
So my question is: which address lines are actually transferred during the address phase? How is the address aligned? Is it possible to change the alignment of the address on AD pins during the address stage?
Thanks,
thefike
