K22FN128 FLL reference clock questions

[isaotakashima]

We will use the MK22FN128 MCU with 20 MHz external crystal, and set core clock to 100 MHz in FEE mode.

I believe that we can set core clock to 100 MHz as below.

- FLL reference clock = 39.0625KHz (= 20 MHz / 512)

- FLL DCO output clock = 39.0625KHz * 2560 = 100MHz.

As you know, the maximum FLL reference frequency range is 39.0625 KHz.

Can I use crystal which 50 ppm frequency tolerance?

Because frequency of crystal is 20 MHz +/- 1 KHz and FLL reference clock is 39.0625 KHz +/- 1.95 Hz, some case exceed 39.0625 KHz.

Then I want to make sure that I can use 50 ppm crystal or not.

Please reply as soon as possible.

Best regards,

Takashima

[jeremyzhou]

Hi Takashima,

I think it's available, however it's necessary to implement stability verification before the manufacturing.
Have a great day,
Ping

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[isaotakashima]

Dear Jeremyzhou,

Thank you for your reply.

I would like to confirm your answer. If you want to say that I should use the crystal which frequency within specification including frequency tolerance, I should use 19.999 MHz 50 ppm crystal or 20 MHz  0 ppm crystal. But I cannot get these parts.

Then I would like NXP to guarantee that I use 20 MHz 50 ppm crystal.

Can NXP do that?

Please reply as soon as possible.

Best regards,

Takashima

[jeremyzhou]

Hi Takashima,

The MCU usually has the extend frequency arrange for clock source, so I think you can give a try.

As I stated above, you also need to do some stability verification testing for it.

Hope it helps.
Have a great day,
Ping

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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[isaotakashima]

Dear Jeremyzhou,

Thank you for your reply.

I don't have good test procedure to confirm stability verification testing.

Best regards,

Takashima