JLink connection on chip MKL46Z256VLH4

[nicolelii]

hello, i was trying to upload my code to my chip (MKL46Z256VLH4) using JLink on MCUXpresso. but when i flash it using debugging mode I got a message saying cannot find target then Error in final launch sequence:

Failed to execute MI command:
-target-select remote localhost:2331

Error message from debugger back end:
localhost:2331: Operation timed out.
Failed to execute MI command:
-target-select remote localhost:2331

Error message from debugger back end:
localhost:2331: Operation timed out.
localhost:2331: Operation timed out.

and i checked the problem on the forum it says it's something wrong with the MCUXpresso IDE update but the IDE i used right now is the latest version. So I don't really know what's the issue. Thank you!

for reference:

VTref is connected to VDD on microcontroller, CLK, IO, RESET, GND are connected accordingly. the VDD of the microcontroller is also powered by a 3.3V external power supply.

[XuZhang]

hi,nicolelii

Thank you for your interest in NXP Semiconductor products and the opportunity to serve you, I will gladly help you with this.

I have done some tests with the FRDM-KL46Z development board, but there is no recurrence of your problem. May I ask if you made the circuit board yourself? The SDK version I use is 2.11.0 and the MCUXpresso IDE version is 11.10. Meanwhile, I have attached my test project so that you can test whether the problem still exists?

BR

Xu Zhang

[nicolelii]

Hello,

I was able to get rid of that issue. However, I got a new error when I was trying to upload code: Error: Failed to halt CPU. and Error: Failed to preserve target RAM @ 0x1FFFE000-0x20005FFF. 

I'm also not using the FRDM-KL46Z board. Instead, I soldered MKL46Z256VLH4 on a breakout board (PA0096) to test chip functionality. 

I connected Vtref to VDD, GND to VSS, SWDIO to PTA3, SWDCLK to PTA0, and RESET to PTA20. I also powered Vtref/VDD using 3.3V power supply.

Thank you!

[XuZhang · Accepted solution]

hi，nicolelii

Please check whether the reset circuit is normal and not in the reset state. It is recommended to check whether the program SWDIO and SWDCLK pins are reused as ordinary pins. At the same time, check whether the hardware circuit welding is normal.

BR

Xu Zhang

[nicolelii]

I checked the voltage at the RESET pin when running, it was at ~3.3V which I think it's fine. I also configured PTA0 and PTA3 as below to make sure it's used as clk and io pins and I'm still getting the same error message. 

// Configure PTA0 as SWD_CLK

PORTA->PCR[0] &= ~PORT_PCR_MUX_MASK;

PORTA->PCR[0] |= PORT_PCR_MUX(7);

// Configure PTA3 as SWD_DIO

PORTA->PCR[3] &= ~PORT_PCR_MUX_MASK;

PORTA->PCR[3] |= PORT_PCR_MUX(7);