I need to measure some small AC signals (~100 uV) and was planning to use the PGA however the PGA seems to introduce a lot of noise in the signal path.
I have a custom board that exhibits this behavior and was also able to write a small Processor Expert program that reproduces the noise on the TWR-K20D72M demo board.
Components used:
ADC, PGA, Vref, PDB
The PDB triggers a conversion in the ADC at a 3000 Hz sample rate.
PGA Gain = 1x
VREF Mode= tight, Regulator=Enabled
ADC Mode=differential, Conversion Time, single sample, short sample time, low-power mode disabled
V+ = V- = 0.6 V
If the PGA is enabled i get about 7 bits of noise
1: 52
2: -51
3: 54
4: -45
5: 53
6: -45
7: 51
8: -54
9: 57
10: -46
11: 55
12: -46
With the PGA disabled and reading DP directly I get about 5 bits of noise:
0: 1
1: 33
2: 19
3: 12
4: 27
5: 28
6: 32
7: 24
8: 28
9: 26
10: 11
11: 24
12: 16
13: 31
On my board I get slightly smaller values.
One thing I noticed is that when the PGA is enabled, every other sample oscillates between positive and negative. So either noise is getting coupled in from the conversion clock or I have something configured wrong (or?).
Any other thoughts? I can attach the PE project if that helps.
-andy
I adjusted the sample rate to a couple of different frequency and the noise followed the same pattern: one sample high and one sample low.
So what I ended up doing was just average the pairs together. This knocked the noise down quite a bit. I then turned on the H/W average function (to 4) and this seemed to do the trick.
With the PGA set to 64 I am now getting 28 uV RMS (compared to almost 1.2 mV RMS of noise before).
I still feel like I am doing something wrong here.
-andy
Hi Andrew,
If you take a look at the K20 datasheet, there are some graphs and tables which may prove useful to you; I would specifically recommend looking at "Table 29. 16-bit ADC with PGA characteristics". The ENOB lines have some great information (which I cannot copy and paste while maintaining formatting).
"Figure 15. Typical ENOB vs. ADC_CLK for 16-bit differential mode" and "Figure 16. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode" are also very informative.
Here is a link to the datasheet I was looking at:
Nicholas,
Thanks for the reply. I had looked at that table and Table 27 as well. One thing that I missed is that most of the specs assume that hardware averaging is on with a minimum of 4 samples. If you turn on hardware averaging then the alternating +/1 50 bits phenomena gets averaged out. I still think there is something funky going on internal to the ADC.
So I think the solution is to simply use hardware averaging:
ADC0_SC3 = (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(0x0u)); // Average = 4
Best Regards,
andy