MCF5329 MSCR_FLEXBUS and MSCR_SDRAM Registers, how do they work in SDR mode?

[TomE]

The MCF5329 can have its pins set up with different drive strengths.

Can anyone help me understand what the MSCR_SDRAM and MSCR_FLEXBUS registers "mean" when using 3.3V SDR? The Reference Manual only seems to document DDR mode.

This is well documented for all pins EXCEPT the Flexbus and SDRAM controller ones.

Typical non-SDRAM/FlexBus pins can be set up as:

• 00 10pF
• 01 20pF
• 10 30pF
• 11 50pF

The MSCR_FLEXBUS and MSCR_SDRAM pins are documented as:

• 00 Half strength 1.8V Mobile DDR.
• 01 Open drain.
• 10 Full strength 1.8V Mobile DDR.
• 11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

That implies the only options for 3.3V SDR chips is the last one.

But I really need 3.3V SDR with a low drive strength like the MCF5235 supported in the programming of its DSCR_EIM register.

So what does it mean to set the register to 00, 01 and 10 when the:

• SVdd pins are connected to 3.3v (and not 1.8 or 2.5),
• The Flexbus is configured for non-DDR, and
• The SDRAM controller is configured for SDR?

If I change the values in the above registers while monitoring what is actually happening on the data bus I find that "00" does drive with a lower strength than when set for "11", so it is doing SOMETHING, but I don't know what.

The MCF5329 manual doesn't give any more help on this.

The MCF53277 manual (and MCF5208 ones) are 99% cut-and-paste from each other, except that the MCF53277 additionally states:

19.6.1    SDR SDRAM Initialization Sequence
   3. Configure the slew rate for the SDRAM external pins in the pin multiplexing

      and control module’s MSCR_SDRAM register if needed.

So that one implies that MSCR_SDRAM can be used in SDR mode. But the documentation of that register in that manual is identical to the one in the MCF5329, and doesn't detail what the settings mean for SDR. That manual forgets to mention changing MSCR_FLEXBUS when changing MSCR_SDRAM - that's an accidental omission.

All manuals have bad cut-and-paste bugs for MSCR_SDRAM too. They all state "SD_CLK mode select control. These bit fields control the strength of the FlexBus lower data pins." which is the description from the PREVIOUS table.

[TomE · Accepted solution]

I received the following complete answer within about 3.5 hours of asking our local distributor. That's and excellent response.

I think there is some confusion info about both MSCR_SDRAM and
MSCR_FLEXBUS registers, please check below interpretation info:
With the MSCR fields (MSCR_x) set to 0b11, the data bus and address bus
will be configured as "2.5V DDR1 or 3.3V CMOS with roughly equal rise
and fall delays", the pads are capable of driving a 50pF load. (high
drive strength )
With the MSCR fields (MSCR_x) set to 0b10, the pads are capable of
driving a 30pF load.
With the MSCR fields (MSCR_x) set to 0b01, the pads are capable of
driving a 20pF load.
With the MSCR fields (MSCR_x) set to 0b00, the pads are capable of
driving a 10pF load. (low drive strength)
We are considering to add this in manual and sorry for the inconvenience
this may cause to you.
And you also could get related info from attached MCF5329 IBIS file.
I abstracted related info below for your reference:
************************************************************************
|                         Model Selector
|***********************************************************************
*
[Model Selector] pad_rfc
| 1.8V VDDE
Pad_rfc_00_1p8  10pF load drive
Pad_rfc_01_1p8  20pF load drive - open drain
Pad_rfc_10_1p8  30pF load drive
Pad_rfc_11_1p8  50pF load drive
Pad_rfc_in_1p8  Input Buffer
| 2.5V VDDE
Pad_rfc_00_2p5  10pF load drive
Pad_rfc_01_2p5  20pF load drive - open drain
Pad_rfc_10_2p5  30pF load drive
Pad_rfc_11_2p5  50pF load drive
Pad_rfc_in_2p5  Input Buffer
| 3.3V VDDE
Pad_rfc_00_3p3  10pF load drive
Pad_rfc_01_3p3  20pF load drive - open drain
Pad_rfc_10_3p3  30pF load drive
Pad_rfc_11_3p3  50pF load drive
Pad_rfc_in_3p3  Input Buffer
************************************************************************
Q1 - What does it mean to run the ports in "Half strength 1.8V low power/mobile DDR" mode with 3.3V SDRAM?
A1 - "Half strength 1.8V low power/mobile DDR" mode with 3.3V SDRAM means low drive strength.
Q2 - What are the actual drive parameters with this setting?
A2 - Low drive strength is 10pF.
Q3 - Is it reliable? Can it be recommended?
A3 - It is reliable.
Q4 - Are there other side-effects of this setting?
A4 - No side-effects.

[TomE]

The previous answers from Freescale fixed the SDRAM controller problem, but showed that the Data Sheets don't give any information about the differences between the different modes.

From the Data Sheet I know we're not exceeding the Drive Capability of the pins when in "High Strength". But we don't have any pins set that way, and the chip defaults to "Second out of Four Strength" out of reset.. We're using "00", "01", and "02" Strengths.

Further questions on "what are the votage and current characteristics" resulted in a simple reply:

Read the IBIS file in the chip page downloadable from Freescale.

This is a data file meant to be read by circuit simulation programs. There are 10,700 lines in it.

It is possible to get some useful information out of this, but it literally takes HOURS.

Here's a few samples:

Below abstrct info from MCF5329 IBIS shows different "Drive Strength" with different current:
[Model]          Pad_rfc_00_2p5 (Drive strength 10pF)
2.5000       25.7801mA           15.6642mA           36.5627mA
[Model]          Pad_rfc_01_2p5 (Drive strength 20pF)
2.5000       37.8790mA           23.0194mA           53.7138mA
[Model]          Pad_rfc_10_2p5 (Drive strength 30pF)
2.5000       56.8199mA           34.5260mA           80.5814mA
[Model]          Pad_rfc_11_2p5 (Drive strength 50pF)
2.5000       94.6989mA           57.5453mA            0.1343A

Normal pins  at 3.3V and "01": pad_fc_33_01:
  [Pulldown]
    0.4000       18.5441mA           11.9133mA           24.9340mA
  [Pullup]
    0.4000      -35.3770mA          -24.9372mA          -46.6793mA

FLEXBUS pins at 3.3V and "00": Pad_rfc_00_3p3:
  [Pulldown]
    0.4000        9.1752mA            5.8891mA           12.3481mA
  [Pullup]
    0.4000      -25.5635mA          -17.8931mA          -34.0260mA

SDRAM  pins  at 3.3V and "10": Pad_rfc_10_3p3:
  [Pulldown]
    0.4000       20.2232mA           12.9807mA           27.2159mA
  [Pullup]
    0.4000      -56.3310mA          -39.4290mA          -74.9783mA

SDRAM  pins  at 3.3V and "11": Pad_rfc_11_3p3:
  [Pulldown]
   0.1000        9.2473mA            5.9932mA           12.3534mA
   0.2000       17.9396mA           11.5904mA           24.0214mA
   0.3000       26.0886mA           16.8013mA           35.0186mA

  [Pullup]
   0.1000      -15.6049mA          -10.9504mA          -20.6701mA
   0.2000      -30.1791mA          -21.1629mA          -40.0335mA
   0.3000      -43.7467mA          -30.6512mA          -58.1251mA

  [Ramp]
  | variable       typ                min                max
  dV/dt_r      1.7328/0.1503n     1.4845/0.2742n   1.9554/0.1002n
  dV/dt_f      1.5712/0.1272n     1.2412/0.2223n   1.8228/88.2325p

[TomE]

There doesn't seem to be any way to change the Drive Strength of the Byte Write lines.

There is a Flexbus drive-strength register that looks like it should change the strength of these,

but it doesn't seem to work when the signals are in SDRAM mode.