Flash accesses (reads/writes) by a bus master other than the core, (DMA controller), or writes to Flash by the core during programming must use the backdoor Flash address of IPSBAR plus an offset of 0x0400_0000. For example, for a DMA transfer from the first location of Flash when IPSBAR is still at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000. Backdoor access to Flash for reads can be made by the bus master, but it takes 2 cycles longer than a direct read of the Flash if using its FLASHBAR address.
Have you seen the example code I posted here:
http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=2749#M2749
It should work fine on the 5213.
Paul.