Bus Error on DMA transfer

[vale]

Hallo,

I'm trying to have a DMA transfer from UART1 to a RX buffer I've allocated.

I'm working on a M52235EVB.

Find below the configuration for the DMA channel 1 I've chosen for such purpose:

  MCF_DMA_DMAREQC |= MCF_DMA_DMAREQC_DMAC1(0x9); //route DMA Channel 1 req to
              //UART1 RX
  MCF_DMA_SAR1=(volatile unsigned long)&MCF_UART1_URB; //DMA Channel 1 source address
              //is UART1 RX buffer
  MCF_DMA_DAR1=(volatile unsigned long) uart->ucpRx_buf;     //DMA Channel 1 destination address
              //is user RX buffer
  MCF_DMA_BCR1=MCF_DMA_BCR_BCR(0x008);   //number of byte to be transferred
  
  MCF_DMA_DCR1 |= //MCF_DMA_DCR_INT |    //enable interrupt on completion of transfer
      MCF_DMA_DCR_EEXT |    //enable external request
      MCF_DMA_DCR_CS |    //forces a single read/write cycle per request
      MCF_DMA_DCR_SSIZE(0x1) |  //1 byte size for source bus cycle
      MCF_DMA_DCR_DINC |    //enable destination increment
      MCF_DMA_DCR_DSIZE(0x1);   //1 byte size for dest bus cycle
     
 }
 
 MCF_SCM_RAMBAR |= (MCF_SCM_RAMBAR_BDE );
  
As you will see, I haven't enabled the interrupt on transfer completion yet. By now I just want to see that

transfer takes place.

Unfortunately no transfer happens and I get this content of DMA Status Register:

DSR1=0x21000008

which indicates a bus error on source.

What is happening? 

Anyone can help me?

Valentina

[mjbcswitzerland]

Valentina

To use DMA you have to ensure that access rights are set up correctly.

Try the following, which is needed for the UART to access from RAM:

// General access set up
GPACR0 = SUP_USER_FULL_ACCESS; // enable peripheral SRAM access

// Access set up per UART channel
PACR_UART1 |= (SUP_USER_FULL_ACCESS SHIFT_LEFT_BY UART1_ACCESS_SHIFT); // enable DMA access to UART1

(SHIFT_LEFT_BY is the sign to shift left. This gets removed when posting...)

// some defines to go with it
#define SUP_USER_FULL_ACCESS 0x04
#define UART0_ACCESS_SHIFT 4
#define PACR_UART1 PACR2
#define UART1_ACCESS_SHIFT 0
#define PACR_UART2 PACR3
#define UART2_ACCESS_SHIFT 4

Regards

[vale]

Hallo Mark,

thanks for your suggestion. Now the DMA transfer is working.

I didn't properly understand the necessity to set the BDE bit in the SCM RAMBAR  register.

What is this for?

The Coldfire Reference Manual says that it is needeed to give module access to SRAM. But what does it mean by "module"?

Thank you for your help

Valentina