Dear sir,
we are facing some issue when the processor P2041 is trying to do this operation while loading the uboot code through debugger we have observed that it is while creating tlb entries for 32 to 36 bit address translation In create_ccsr_new_tlb section it is raising an excpetion “FPUnavailable” from 0xfffff220 and going to expetion handler 0xeff40800.
In some cases it also raises expetion “InstructionTLBError” from 0xfffff224 and goes to handler 0xeff40e00.
We are stuck at this point. we are using our own custom board similar to p2041rdb,How to proceed ahead ?
PFA for the screenshots of Codewarrior Debugger.
Hi
I don't see any attached file. Can you try again ?
Regards
Sinan Akman
desr sir
thanks for your reply
i had lowered all the clock configuration in the rcw now it is passing this section and it is hanging around this part i am getting some junk in the serial console also now how to set the baud rate in the u-boot code or why am i getting some junk data instead of soc information that i am getting in eval board