The following code sequence describes how to move from FEI mode to PEE mode until the 8MHz crystal
reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in FEI mode out of
reset, this example also shows how to initialize the MCG for PEE mode out of reset.
1. First, FEI must transition to FBE mode:
a) MCGC2 = 0x36 (%00110110)
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) Block Interrupts (If applicable by setting the interrupt bit in the CCR).
d) MCGC1 = 0xB8 (%10111000)
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128.
NOTE
8MHz / 128 = 62.5 kHz which is greater than the 31.25 kHz to 39.0625 kHz
range required by the FLL. Therefore after the transition to FBE is
complete, software must progress through to BLPE mode immediately by
setting the LP bit in MCGC2.
– IREFS (bit 2) cleared to 0, selecting the external reference clock
e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
source for the reference clock
f) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference
clock is selected to feed MCGOUT
2. Then, FBE mode transitions into BLPE mode:
a) MCGC2 = 0x3E (%00111110)
– LP (bit 3) in MCGC2 to 1 (BLPE mode entered)
NOTE
There must be no extra steps (including interrupts) between steps 1d and 2a.
b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR).
c) MCGC1 = 0x98 (%10011000)
– RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1
MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV
does not matter because both the FLL and PLL are disabled. Changing them only sets up the
the dividers for PLL usage in PBE mode
d) MCGC3 = 0x44 (%01000100)
– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the
MCG for PLL usage in PBE mode
– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1MHz reference * 16 = 16 MHz.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS
clock is the PLL
3. Then, BLPE mode transitions into PBE mode:
a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode
b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
4. Last, PBE mode transitions into PEE mode:
a) MCGC1 = 0x18 (%00011000)
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
system clock source
– Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is
selected to feed MCGOUT in the current clock mode
b) Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16,
MCGOUT = [(8 MHz / 8) * 16] / 1 = 16MHz, and the bus frequency isMCGOUT / 2, or 8 MHz
8.4.6 External Reference Clock
The MCG module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz
in all modes. When ERCLKEN is set, the external reference clock signal will be presented as
MCGERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL or PLL and will only be used as MCGERCLK. In these modes, the
frequency can be equal to the maximum frequency the chip-level timing specifications will support (see
the Device Overview chapter).
which seems ok Because, if we calculate
Max. frequency FLL supports is 39.0625 kHz and Max. RDIV value is 2^7 = 128.
So Fext = 39.0625 * 128 * (10^3) = 5 Mhz.
So, I was thinking in correct way. It must be 4 Mhz or 5Mhz
What is your opinion
Waiting for your reply.
Sangram
1. First, FEI must transition to FBE mode:
MCGC1 = 0xB8 (%10111000)
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL
– IREFS (bit 2) cleared to 0, selecting the external reference clock
In FBE mode itself they mentioned that FLL frequency I/p must be in 31.25khz to 39.0625. kHz
How is it possible then to go to BLPE or directly to PBE mode.
What RAMABH posted is correct or wrong ?
Please, answer these questions.
Best regards
Sangram
SOPT1_COPT = 0; /* disable COP */ SOPT2_MCSEL = 1; /* enable MCLK. MCLK = BUSCLK/2 */ Ports_Init(); EnableInterrupts; /* enable interrupts */ /* Configure MCG to produce a 16MHz bus clock from a 4MHz external crystal via FLL */ /* set up external oscillator */ MCGC2_RANGE = 1; MCGC2_ERCLKEN=1; MCGC2_EREFS = 1; MCGC2_HGO = 1; while (!MCGSC_OSCINIT); /* Change the reference divider */ MCGC1_RDIV = 0b111; /* Select Reference Clock */ MCGC1_IREFS = 0; /* wait for Reference Status bit to update */ while (!MCGSC_IREFST); /* Wait for LOCK bit to set */ while (!MCGSC_LOCK); /* Select the Bus Divider */ MCGC2_BDIV = 0b00; /* Turn on Clock Monitor */// MCGC3_CME = 1; MCG_MODE = FEE;
SOPT1_COPT = 0; /* disable COP */ SOPT2_MCSEL = 1; /* enable MCLK. MCLK = BUSCLK/2 */ Ports_Init(); EnableInterrupts; /* enable interrupts */ /* Configure MCG to produce a 20MHz bus clock from a 4MHz external crystal via PLL */ /* Select High Range, High Gain, Bus divided by 1, Oscillator, ERCLK enabled */ MCGC2 = 0x36; while (!MCGSC_OSCINIT); /* Select External Clock as bus clock source, Reference divided by 8, Reference = external */ MCGC1 = 0xB8; /* wait for Reference Status bit to update */ while (!MCGSC_IREFST); /* Wait for clock status bits to update */ while (MCGSC_CLKST != 0b10); /* now in FBE mode */ /* Enter BLPE mode */// MCGC2_LP=1; /* now in BLPE mode */ /* Change RDIV for PLL reference */ MCGC1 = 0x90; /* Select the VCO divider and PLL */ MCGC3 = 0x4A; /* Enter PBE mode */// MCGC2_LP=0; /* Wait for PLL status to update */ while (!MCGSC_PLLST); /* now in PBE mode */ /* Wait for LOCK bit to set */ while (!MCGSC_LOCK); /* Enter PEE mode */ MCGC1 = 0x10; /* Wait for Clock status to indicate PLL output */ while (MCGSC_CLKST != 0b11); MCG_MODE = PEE; /* Switch on Clock monitor */ MCGC3_CME = 1; /* Enable LOL IRQ */ MCGC3_LOLIE = 1;