Dear team,
I would like to ask about PCIe reference clock of i.MX6Q.
In your latest i.MX6DQ Hardware development guide(IMX6DQ6SDLHDG, Rev.2.), it is stated as below in Table 2-10 ‘PCIe recommendations’.
“1. An external PCIe reference clock generator is recommended. i.MX differential clock is not compliant with PCIe standard.
i.MX differential clock does not meet PCIe compliance standards”
Now my customer is using the PCIe interface on their board, and CLK1_N/P from i.MX6 are used for external FPGA as a reference clock.
After reading the latest HDG, they have a concern on the PCIe refClock use.
Should they change their current design into using an external ref clock?
Thanks,
Miyamoto
