MPC5746C LINFlexD_1 DMARXE DMATXE

[cholland]

Hi,

I am having a similar problem as this post.

IVOR 1 when writing to LINFlex DMATXE  

DMA Mode on LIN0 works fine.

I tried doing what the post suggested, but it's not working for me.

I don't see the offset table in the RM.

LINFlexD_1.UARTCR.R = 1; // set the UART bit first to be able to write the other bits
LINFlexD_1.UARTCR.B.WL1 = 0; // 8 bits data when PCE = 0 or 8 bits data + parity when PCE = 1
LINFlexD_1.UARTCR.B.WL0 = 1; // 8 bits data when PCE = 0 or 8 bits data + parity when PCE = 1
LINFlexD_1.UARTCR.B.TxEn = 1; // Transmitter Enabled
LINFlexD_1.UARTCR.B.RxEn = 1; // Receiver Enabled
LINFlexD_1.UARTCR.B.RFBM = 1; // UART Rx FIFO Mode Enabled (DMA requirement)
LINFlexD_1.UARTCR.B.TFBM = 1; // UART Tx FIFO Mode Enabled (DMA requirement)
//LINFlexD_1.DMARXE.R = 0x0000ffff; // Enable DMA //see https://community.nxp.com/thread/463696
//LINFlexD_1.DMATXE.R = 0x0000ffff; // Enable DMA //see https://community.nxp.com/thread/463696
//(*(vuint32_t *) (0xFBE8C000UL + (32 * 23)) ) = 0x0000FFFFUL;
//(*(vuint32_t *) (0xFBE8C000UL + (32 * 24)) ) = 0x0000FFFFUL;
//LINFlexD_1.IFCR[3].R = 0x0000ffff; // Enable DMA //see https://community.nxp.com/thread/463696
//LINFlexD_1.IFCR[4].R = 0x0000ffff; // Enable DMA //see https://community.nxp.com/thread/463696
LINFlexD_1.LINIER.B.DRIE = 0; // Disable RX Interrupt (DMA requirement)
LINFlexD_1.LINIER.B.DTIE = 0; // Disable Tx Interrupt (DMA requirement)

[PetrS]

Hi,

offsets are mentioned in module's Memory map and register description chapter 46.5, see Table 46-18

following instruction should work

(*(vuint32_t *) (0xFBE8C000UL + (0x58)) ) = 0x1; // Enable DMA TX
(*(vuint32_t *) (0xFBE8C000UL + (0x5C)) ) = 0x1; // Enable DMA RX

Below lines should work too, depends on header file

LINFlexD_1.IFCR[3].R = 0x1; // Enable DMA TX

LINFlexD_1.IFCR[4].R = 0x1; // Enable DMA RX

Note: there are just 2 DMA request per module, so only lowest bit are implemented.

BR, Petr