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i.MX 7Dual power sequence measurement

Question asked by justin hsieh on Jul 16, 2020

Dear Team,

According i.MX 7Dual datasheet, it shows timing spec. as below,

 

T1 Time from SVNS power stable to other power rails start to ramp, minimal delay is 2ms,
no max delay requirement.

power sequence

Can you kindly clearify T1 means that 90%*VDD_SNVS_IN to 10%*NVCCGPIO or 90%*NVCCGPIO?

 

Thanks, 

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