i.MX 7Dual power sequence measurement

[justin_hsieh]

Dear Team,

According i.MX 7Dual datasheet, it shows timing spec. as below,

T1 Time from SVNS power stable to other power rails start to ramp, minimal delay is 2ms,
no max delay requirement.

Can you kindly clearify T1 means that 90%*VDD_SNVS_IN to 10%*NVCCGPIO or 90%*NVCCGPIO?

Thanks, 

[art]

Here T1 means 90% VDD_SNVS_IN to 10% NVCCGPIO and other voltages except of NVCC_DRAM and NVCC_DRAM_CKE.

Best Regards,
Artur