I'm in the process of implementing the JTAG interface to our LS1028A application. Figure 36 of the LS1028A Design Checklist (AN12028) shows a SPDT switch in an unconnected state with the following note:
2. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, ensure this switch is closed.
The note does not mention which terminal it should be closed to. Should it be closed to the PORESET_B line or to the pull up to OVDD?
If it should be closed to a specific connection, what is the purpose or function for closing in the opposite direction?
We are also interested in interfacing the JTAG with another networking PHY device that has a JTAG port. That device has a TRSTn pin as an input that requires a pull down for normal operation. Figure 36 has a pull up for the input pin where other TRST_B sources would interface. Does this indicate the TRST interfaces of the networking PHY and LS1028A are incompatible, or does there just need to be a logic inverter?
Ideally, we would like to have a method where the switch is not being used due to the environment's vibration.
Figure 36 is attached.