We have a custom board where Serdes lane A of a TQMLS1012AL-AA module (contains a QorIQ LS1012a) is connected to a gigabit Ethernet switch (KSZ9567S). The Ethernet switch is working in U-Boot (tftp too) when using the internal clock, but when switching to an external reference clock (by only changing the RCW), the Serdes lane A becomes unable to finish auto-negotiation.
Our Phy is configured in the following scheme:
When using the external reference clock, the RCW is configured as follows:
The output of our 100 MHz reference clock measured on the traces going to the SD_REF_CLK+/- pins, measured with persistence (for about half a minute) on on a scope:
The exact values of the RCW in both cases can be seen in the attached files: U-boot_extClkSerdesRegs.txt and U-boot_intClkSerdesRegs.txt. The values of all of the Serdes registers (big endian) and the PFE MDIO register (clause 22) as well as some of the indirect registers from the KSZ9567S switch, printed from U-boot are also available in the attached files. The exact differences in the register values were later added to the files. Note that U-boot is exactly the same for both attachments, only the RCW is different.
The problem when using the external reference clock is that no page is received, the auto negotiation never completes.
PCIe on SerDes lane B, also mapped to PLL 1 (same as SerDes lane A), works when booting in Linux (or a connected PCIe WiFi module is recognized by OpenWrt). From the registers (see attachments), the PLL (PLL 1) is in application mode, running without errors and is also locked.
We have also tested both RCW's on the MBLS1012AL.0200 board (a reference board for the TQMLS1012AL-AA module), the same Serdes lane (A) is connected to a DP83867IS on the reference design. A 100 MHz reference clock is also connected to the SD_REF_CLK+/- pins on this reference design. The DP83867IS works for both RCW's on this design.
Is there any reason that the external clock configuration should not work with our configuration?
The problem has been solved:
Our PCIe clock generator had a spread of -0.5%.
The problem has been solved:
Our PCIe clock generator had a spread of -0.5%.
