LPC55S69 : Sensitivity of GPIO pins

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LPC55S69 : Sensitivity of GPIO pins

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EugeneHiihtaja
Senior Contributor I

Hello !

We have plan to use GPIO pins as part of GINT0/1 group for wakeup MCU from Power-Down mode.

But it is not so clear from DS what kind of sensivity those pins have ?

What kind of minimal edge can be detected, is any debounce or glitch filters there and etc.

Do you have extra info about it ?

Regards,

Eugene

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Sabina_Bruce
NXP Employee
NXP Employee

Hello Eugene,

In the datasheet the pin characteristics are described.

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The high level input voltage is the voltage level necessary to send to the device for it to read a logic high. The low level input voltage is the voltage level necessary to send to the device for it to read a logic low. Wake up pins can be configured as rising or falling edge. 

Best Regards,

Sabina

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